YLCDRSK2378 Renesas Electronics America, YLCDRSK2378 Datasheet - Page 767

• Manufacturer Part Number: YLCDRSK2378
• Description: KIT DEV EVAL H8S/2378 LCD
• Manufacturer: Renesas Electronics America
• Series: H8®r

Specifications of YLCDRSK2378

• Main Purpose: Displays, LCD Controller
• Embedded: Yes, MCU, 16-Bit
• Utilized Ic / Part: YLCDRSK2378
• Primary Attributes: 5.7" QVGA, Touch Screen
• Secondary Attributes: Source Code on CD, Debugging Requires Emulator Cable E10A USB/JTAG
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Bit
5
4
3
Bit Name
TE
RE
MPIE
Initial Value
0
0
0
R/W
R/W
R/W
R/W
Section 15 Serial Communication Interface (SCI, IrDA)
Description
Transmit Enable
When this bit s set to 1, transmission is enabled. In
this state, serial transmission is started when
transmit data is written to TDR and the TDRE flag
in SSR is cleared to 0. SMR setting must be
performed to decide the transfer format before
setting the TE bit to 1.
The TDRE flag in SSR is fixed at 1 if transmission
is disabled by clearing this bit to 0.
Receive Enable
When this bit is set to 1, reception is enabled.
Serial reception is started in this state when a start
bit is detected in asynchronous mode or serial clock
input is detected in clocked synchronous mode.
SMR setting must be performed to decide the
transfer format before setting the RE bit to 1.
Clearing the RE bit to 0 does not affect the RDRF,
FER, PER, and ORER flags, which retain their
states.
Multiprocessor Interrupt Enable (enabled only when
the MP bit in SMR is 1 in asynchronous mode)
When this bit is set to 1, receive data in which the
multiprocessor bit is 0 is skipped, and setting of the
RDRF, FER, and ORER status flags in SSR is
prohibited. On receiving data in which the
multiprocessor bit is 1, this bit is automatically
cleared and normal reception is resumed. For
details, refer to section 15.5, Multiprocessor
Communication Function.
When receive data including MPB = 0 in SSR is
received, receive data transfer from RSR to RDR,
receive error detection, and setting of the RDRF,
FER, and ORER flags in SSR , is not performed.
When receive data including MPB = 1 is received,
the MPB bit in SSR is set to 1, the MPIE bit is
cleared to 0 automatically, and generation of RXI
and ERI interrupts (when the TIE and RIE bits in
SCR are set to 1) and FER and ORER flag setting
is enabled.
Rev.7.00 Mar. 18, 2009 page 699 of 1136
REJ09B0109-0700