TMPM362F10FG Toshiba, TMPM362F10FG Datasheet - Page 89

• Manufacturer Part Number: TMPM362F10FG
• Description: 32BIT MICROCONTROLLER
• Manufacturer: Toshiba
• Series: TX03r

Specifications of TMPM362F10FG

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 64MHz
• Connectivity: I²C, Microwire, SIO, SPI, SSP, UART/USART
• Peripherals: DMA, WDT
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 16x10b
• Package / Case: 144-LQFP
• Processor Series: TX03
• Core: ARM Cortex M3
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): 1024K
• Rom Type: Flash
• Ram (kbytes): 64K
• Number Of Pins: 144
• Package: LQFP(20x20)
• Vcc: 3V
• Cpu Mhz: 64
• Ssp (ch) Spi: 1
• I2c/sio (ch): 5
• Uart/sio (ch): 12
• Usb: -
• Can: -
• Ethernet: -
• External Bus Interface: Y
• Cs/wait Controller (ch): 4
• Dma Controller: 2
• 10-bit Da Converter: -
• 10-bit Ad Converter: 16
• 12-bit Ad Converter: -
• 16-bit Timer / Counter: 16
• Motor / Igbt Control: -
• Real Time Clock: 1
• Watchdog Timer: Y
• Osc Freq Detect: -
• Clock Gear: Y
• Low-power Hold Function: Y
• Remote Control Interface: Y
• Hardware Cec Controller: Y
• Comparators: -
• Low-voltage Detector: -
• Etm Hardware Trace: 4-bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Operating Temperature: -
• Number Of I /o: -
• Eeprom Size: -
• Oscillator Type: -
• Lead Free Status / Rohs Status: Details
• Other names: Q5704184A

7.1.2.2
rupt service routine. This is called "pre-emption".
(1)
(2)
(3)
(4)
When an exception occurs, the CPU suspends the currently executing process and branches to the inter-
Exception Handling and Branch to the Interrupt Service Routine (Pre-emption)
stack in the following order :
the state of the stack after the register contents have been pushed.
tor table is located at address 0x0000_0000 in the Code area.By setting the Vector Table Offset Reg-
ister, you can place the vector table at any address in the Code or SRAM space.
the CPU handles the higher priority exception first. This is called "late-arriving".
sponding ISR, but the CPU does not newly push the register contents to the stack.
When the CPU detects an exception, it pushes the contents of the following eight registers to the
The SP is decremented by eight words by the completion of the stack push.The following shows
The CPU enables instruction to fetch the interrupt processing with data store to the register.
Prepare a vector table containing the top addresses of ISRs for each exception.After reset, the vec-
The vector table should also contain the initial value of the main stack.
If the CPU detects a higher priority exception before executing the ISR for a previous exception,
A late-arriving exception causes the CPU to fetch a new vector address for branching to the corre-
The vector table is configured as shown below.
Stacking
fetching an ISR
Late-arriving
Vector table
・ Program Counter (PC)
・ Program Status Register (xPSR)
・ r0 to r3
・ r12
・ Link Register (LR)
Old SP →
SP →
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xPSR
PC
r12
LR
r3
r2
r1
r0
TMPM362F10FG