TMPM362F10FG Toshiba, TMPM362F10FG Datasheet - Page 103

• Manufacturer Part Number: TMPM362F10FG
• Description: 32BIT MICROCONTROLLER
• Manufacturer: Toshiba
• Series: TX03r

Specifications of TMPM362F10FG

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 64MHz
• Connectivity: I²C, Microwire, SIO, SPI, SSP, UART/USART
• Peripherals: DMA, WDT
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 16x10b
• Package / Case: 144-LQFP
• Processor Series: TX03
• Core: ARM Cortex M3
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): 1024K
• Rom Type: Flash
• Ram (kbytes): 64K
• Number Of Pins: 144
• Package: LQFP(20x20)
• Vcc: 3V
• Cpu Mhz: 64
• Ssp (ch) Spi: 1
• I2c/sio (ch): 5
• Uart/sio (ch): 12
• Usb: -
• Can: -
• Ethernet: -
• External Bus Interface: Y
• Cs/wait Controller (ch): 4
• Dma Controller: 2
• 10-bit Da Converter: -
• 10-bit Ad Converter: 16
• 12-bit Ad Converter: -
• 16-bit Timer / Counter: 16
• Motor / Igbt Control: -
• Real Time Clock: 1
• Watchdog Timer: Y
• Osc Freq Detect: -
• Clock Gear: Y
• Low-power Hold Function: Y
• Remote Control Interface: Y
• Hardware Cec Controller: Y
• Comparators: -
• Low-voltage Detector: -
• Etm Hardware Trace: 4-bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Operating Temperature: -
• Number Of I /o: -
• Eeprom Size: -
• Oscillator Type: -
• Lead Free Status / Rohs Status: Details
• Other names: Q5704184A

7.5.2.4
7.5.2.5
7.5.2.6
enter the ISR.
what is recommended at the service routine programming and how the source is cleared.
(1)
(2)
The CPU detects an interrupt request with the highest priority.
On detecting an interrupt, the CPU pushes the contents of PC, PSR, r0-r3, r12 and LR to the stack then
An ISR requires specific programming according to the application to be used. This section describes
Detection by CPU
CPU processing
Interrupt Service Routine (ISR)
tex-M3 core automatically pushes the contents of PC, PSR, r0-r3, r12 and LR to the stack. No extra
programming is required for them.
ISR is being executed. We recommend you to push the contents of general-purpose registers that
might be rewritten.
with the CG Interrupt Request Clear (CGICRCG) Register.
cleared at its source. Therefore, the interrupt source must be cleared. Clearing the interrupt source au-
tomatically clears the interrupt request signal from the clock generator.
ue in the CGICRCG register. When an active edge occurs again, a new interrupt request will be detec-
ted.
An ISR normally pushes register contents to the stack and handles an interrupt as required. The Cor-
Push the contents of other registers if needed.
Interrupt requests with higher priority and exceptions such as NMI are accepted even when an
If an interrupt source is used for clearing a standby mode, each interrupt request must be cleared
If an interrupt source is set as level-sensitive, an interrupt request continues to exist until it is
If an interrupt is set as edge-sensitive, clear an interrupt request by setting the corresponding val-
Pushing during ISR
Clearing an interrupt source
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TMPM362F10FG