TMPM362F10FG Toshiba, TMPM362F10FG Datasheet - Page 554

• Manufacturer Part Number: TMPM362F10FG
• Description: 32BIT MICROCONTROLLER
• Manufacturer: Toshiba
• Series: TX03r

Specifications of TMPM362F10FG

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 64MHz
• Connectivity: I²C, Microwire, SIO, SPI, SSP, UART/USART
• Peripherals: DMA, WDT
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 16x10b
• Package / Case: 144-LQFP
• Processor Series: TX03
• Core: ARM Cortex M3
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): 1024K
• Rom Type: Flash
• Ram (kbytes): 64K
• Number Of Pins: 144
• Package: LQFP(20x20)
• Vcc: 3V
• Cpu Mhz: 64
• Ssp (ch) Spi: 1
• I2c/sio (ch): 5
• Uart/sio (ch): 12
• Usb: -
• Can: -
• Ethernet: -
• External Bus Interface: Y
• Cs/wait Controller (ch): 4
• Dma Controller: 2
• 10-bit Da Converter: -
• 10-bit Ad Converter: 16
• 12-bit Ad Converter: -
• 16-bit Timer / Counter: 16
• Motor / Igbt Control: -
• Real Time Clock: 1
• Watchdog Timer: Y
• Osc Freq Detect: -
• Clock Gear: Y
• Low-power Hold Function: Y
• Remote Control Interface: Y
• Hardware Cec Controller: Y
• Comparators: -
• Low-voltage Detector: -
• Etm Hardware Trace: 4-bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Operating Temperature: -
• Number Of I /o: -
• Eeprom Size: -
• Oscillator Type: -
• Lead Free Status / Rohs Status: Details
• Other names: Q5704184A

16.3
Registers
16.3.8
31
30
29-26
25
24
23-16
15-8
7-0
bit symbol
After reset
bit symbol
After reset
bit symbol
After reset
bit symbol
After reset
Bit
RMCLIEN
RMCEDIEN
−
RMCLD
RMCPHM
−
RMCLL[7:0]
RMCDMAX[7:0]
RMCxRCR2(Receive Control Register 2)
Bit Symbol
RMCLIEN
31
23
15
0
0
1
7
1
-
R/W
R/W
R
R/W
R/W
R
R/W
R/W
Type
RMCEDIEN
30
22
14
0
0
1
6
1
-
Leader detection interrupt
0: Not generated
1: Generated
Remote control input falling edge interrupt
0: Not generated
1: Generated
Read as 0.
Receiving remote control signal with or without leader
0: Disabled
1: Enabled
Receiving a remote control signal by a phase modulation
0: Not receiving a remote control signal by a phase modulation. (receive by a cycle modulation)
1: Receive remote control signal by a fixed-frequency pulse modulation.
To receive a fixed-frequency remote control signal by a pulse modulation, set this bit to "1".
Read as 0.
Excess low width that triggers reception completion and interrupt generation.
0000_0000 to 1111_1110: Reception completion and interrupt generation at <RMCLL> × 1/fs [s].
1111_1111: not to use as the trigger
Maximum data bit cycle that triggers reception completion and interrupt generation.
0000_0000 to 1111_1110: Reception completion and interrupt generation at <RMCDMAX> × 1/fs [s].
1111_1111: not to use as the trigger
29
21
13
0
0
1
5
1
-
-
Page 530
28
20
12
0
0
1
4
1
-
-
RMCDMAX
RMCLL
27
19
11
0
0
1
3
1
-
-
Function
26
18
10
0
0
1
2
1
-
-
RMCLD
25
17
0
0
9
1
1
1
-
TMPM362F10FG
RMCPHM
24
16
0
0
8
1
0
1
-