TMPM362F10FG Toshiba, TMPM362F10FG Datasheet - Page 62
TMPM362F10FG
Manufacturer Part Number
TMPM362F10FG
Description
32BIT MICROCONTROLLER
Manufacturer
Toshiba
Series
TX03r
Datasheet
1.TMPM362F10FG.pdf
(744 pages)
Specifications of TMPM362F10FG
Core Processor
ARM® Cortex-M3™
Core Size
32-Bit
Speed
64MHz
Connectivity
I²C, Microwire, SIO, SPI, SSP, UART/USART
Peripherals
DMA, WDT
Program Memory Size
1MB (1M x 8)
Program Memory Type
FLASH
Ram Size
64K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 16x10b
Package / Case
144-LQFP
Processor Series
TX03
Core
ARM Cortex M3
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2
Product Summaries
Summary
Lead Free
Yes
Rohs Compatible Product(s)
Available
Rom (kbytes)
1024K
Rom Type
Flash
Ram (kbytes)
64K
Number Of Pins
144
Package
LQFP(20x20)
Vcc
3V
Cpu Mhz
64
Ssp (ch) Spi
1
I2c/sio (ch)
5
Uart/sio (ch)
12
Usb
-
Can
-
Ethernet
-
External Bus Interface
Y
Cs/wait Controller (ch)
4
Dma Controller
2
10-bit Da Converter
-
10-bit Ad Converter
16
12-bit Ad Converter
-
16-bit Timer / Counter
16
Motor / Igbt Control
-
Real Time Clock
1
Watchdog Timer
Y
Osc Freq Detect
-
Clock Gear
Y
Low-power Hold Function
Y
Remote Control Interface
Y
Hardware Cec Controller
Y
Comparators
-
Low-voltage Detector
-
Etm Hardware Trace
4-bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Operating Temperature
-
Number Of I /o
-
Eeprom Size
-
Oscillator Type
-
Lead Free Status / Rohs Status
Details
Other names
Q5704184A
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
TMPM362F10FG
Manufacturer:
Freescale
Quantity:
488
- Current page: 62 of 744
- Download datasheet (8Mb)
6.2
Registers
6.2.4
31-18
17
16
15-10
9
8
7-3
2-0
bit symbol
After reset
bit symbol
After reset
bit symbol
After reset
bit symbol
After reset
Bit
−
PTKEEP
DRVE
−
RXTEN
RXEN
−
STBY[2:0]
CGSTBYCR (Standby control register)
Bit Symbol
Note:I/O Ports which hold their state when CGSTBYCR<PTKEEP> is changed from "0" to "1" are all port ex-
31
23
15
0
0
0
7
0
-
-
-
-
cept for port I, J, L, M and N. In regarding to release CGSTBYCR<PTKEEP>, refer to section of "Back-
up module".
R
R/W
R/W
R
R/W
R/W
R
R/W
Type
30
22
14
0
0
0
6
0
-
-
-
-
Read as "0".
I/O port control in the Backup mode.
0: Output the contents of output latch.
1: Hold the port state when CGSTBYCR<PTKEEP> is changed from "0" to "1".
Pin status in STOP mode (note)
0: Inactive
1: Active
Read as "0".
Low-speed oscillator operation after releasing the STOP mode.
0: Stop
1: Oscillation
High-speed oscillator operation after releasing the STOP mode.
0: Stop
1: Oscillation
Read as "0".
Low power consumption mode
000: Reserved
001: STOP
010: SLEEP
011: IDLE2
100: Reserved
101: BACKUP STOP
110: BACKUP SLEEP
111: IDLE1
29
21
13
0
0
0
5
0
-
-
-
-
Page 38
28
20
12
0
0
0
4
0
-
-
-
-
27
19
11
Function
0
0
0
3
0
-
-
-
-
26
18
10
0
0
0
2
0
-
-
-
PTKEEP
RXTEN
STBY
25
17
0
0
9
0
1
1
-
TMPM362F10FG
DRVE
RXEN
24
16
0
0
8
1
0
1
-
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