TMPM362F10FG Toshiba, TMPM362F10FG Datasheet - Page 567
TMPM362F10FG
Manufacturer Part Number
TMPM362F10FG
Description
32BIT MICROCONTROLLER
Manufacturer
Toshiba
Series
TX03r
Datasheet
1.TMPM362F10FG.pdf
(744 pages)
Specifications of TMPM362F10FG
Core Processor
ARM® Cortex-M3™
Core Size
32-Bit
Speed
64MHz
Connectivity
I²C, Microwire, SIO, SPI, SSP, UART/USART
Peripherals
DMA, WDT
Program Memory Size
1MB (1M x 8)
Program Memory Type
FLASH
Ram Size
64K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 16x10b
Package / Case
144-LQFP
Processor Series
TX03
Core
ARM Cortex M3
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2
Product Summaries
Summary
Lead Free
Yes
Rohs Compatible Product(s)
Available
Rom (kbytes)
1024K
Rom Type
Flash
Ram (kbytes)
64K
Number Of Pins
144
Package
LQFP(20x20)
Vcc
3V
Cpu Mhz
64
Ssp (ch) Spi
1
I2c/sio (ch)
5
Uart/sio (ch)
12
Usb
-
Can
-
Ethernet
-
External Bus Interface
Y
Cs/wait Controller (ch)
4
Dma Controller
2
10-bit Da Converter
-
10-bit Ad Converter
16
12-bit Ad Converter
-
16-bit Timer / Counter
16
Motor / Igbt Control
-
Real Time Clock
1
Watchdog Timer
Y
Osc Freq Detect
-
Clock Gear
Y
Low-power Hold Function
Y
Remote Control Interface
Y
Hardware Cec Controller
Y
Comparators
-
Low-voltage Detector
-
Etm Hardware Trace
4-bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Operating Temperature
-
Number Of I /o
-
Eeprom Size
-
Oscillator Type
-
Lead Free Status / Rohs Status
Details
Other names
Q5704184A
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
TMPM362F10FG
Manufacturer:
Freescale
Quantity:
488
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16.4.1.4
16.4.1.5
16.4.1.6
RMCxRCR3 and RMCxRCR4 registers, RMC is ready for reception. Detecting a leader initiates reception.
width is shorter than a maximum low width of leader detection specified in the RMCxRCR1 <RMCLLMAX
[7:0]> bits. RMC keeps receiving data until the final data bit is received.
ta bit determination of 0 or 1 are applied regardless of whether a signal has a leader or not.
By enabling the RMCxREN <RMCREN> bit after configuring the RMCxRCR1, RMCxRCR2,
RMC stops reception by clearing the RMCxREN <RMCREN> bit to "0" (reception disabled).
Clearing this bit during reception stops reception immediately and the received data is discarded.
Setting RMCxRCR2 <RMCLD> enables RMC to receive signals with or without a leader.
By setting RMCxRCR2 <RMCLD>, RMC starts receiving data if it recognizes a signal of which low
If RMCxRCR2 <RMCLD> is enabled, the same settings of error detection, reception completion and da-
Thus receivable remote control signals are limited.
Note:Changing the configurations of the RMCxRCR1, RMCxRCR2, RMCxRCR3 and RMCxRCR4 regis-
Enabling Reception
Stopping Reception
Receiving Remote Control Signal without Leader in Waiting Leader
Waiting for leader
RMCxRCR2<RMCLD> = 1
ters during reception may harm their proper operation. Be careful if you change them during reception.
Leader waveform
Maximum data bit cycle <RMCDMAX[7:0]>
Minimum low width <RMCLLMIN[7:0]>
Maximum data bit cycle is detected if a signal stays
low shorter than specified and longer than a maximum
data bit cycle.
Page 543
RMC starts receiving data by receiving a signal which
is less than the minimum low pulse width.
TMPM362F10FG
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