TMPM362F10FG Toshiba, TMPM362F10FG Datasheet - Page 466

• Manufacturer Part Number: TMPM362F10FG
• Description: 32BIT MICROCONTROLLER
• Manufacturer: Toshiba
• Series: TX03r

Specifications of TMPM362F10FG

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 64MHz
• Connectivity: I²C, Microwire, SIO, SPI, SSP, UART/USART
• Peripherals: DMA, WDT
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 16x10b
• Package / Case: 144-LQFP
• Processor Series: TX03
• Core: ARM Cortex M3
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): 1024K
• Rom Type: Flash
• Ram (kbytes): 64K
• Number Of Pins: 144
• Package: LQFP(20x20)
• Vcc: 3V
• Cpu Mhz: 64
• Ssp (ch) Spi: 1
• I2c/sio (ch): 5
• Uart/sio (ch): 12
• Usb: -
• Can: -
• Ethernet: -
• External Bus Interface: Y
• Cs/wait Controller (ch): 4
• Dma Controller: 2
• 10-bit Da Converter: -
• 10-bit Ad Converter: 16
• 12-bit Ad Converter: -
• 16-bit Timer / Counter: 16
• Motor / Igbt Control: -
• Real Time Clock: 1
• Watchdog Timer: Y
• Osc Freq Detect: -
• Clock Gear: Y
• Low-power Hold Function: Y
• Remote Control Interface: Y
• Hardware Cec Controller: Y
• Comparators: -
• Low-voltage Detector: -
• Etm Hardware Trace: 4-bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Operating Temperature: -
• Number Of I /o: -
• Eeprom Size: -
• Oscillator Type: -
• Lead Free Status / Rohs Status: Details
• Other names: Q5704184A

13.6
Frame Format
13.6.2
Figure 13-5 SPI frame format (continuous transfer,<SPO>="0" & <SPH>="0")
mat is that the <SPO> and <SPH> bits in the SSPCR0 register can be used to set the SPCLK operation timing.
Figure 13-4 SPI frame format (single transfer, <SPO>="0" & <SPH>="0")
Note 1: When transmission is disable, SPDO terminal doesn't output and is high impedance status. This terminal needs
Note 2: SPDI terminal is always input and internal gate is open. In case of transmission signal will be high impedance sta-
The SPI interface has 4 lines. SPFSS is used for slave selection. One of the main features of the SPI for-
SSPCR0 <SPO> is used to set the level at which SPCLK in idle state is held.
SSPCR0 <SPH> is used to select the clock edge at which data is latched.
SPI frame format
to add suitable pull-up/down resistance to valid the voltage level.
tus, this terminal needs to add suitable pull-up/down resistance to valid the voltage level.
SPFSS
SPDO
SPDI
SPCLK
SPCLK
SPFSS
SPDO
SPDI
0
1
LSB
LSB
Hi-Z(Note1
Hi-Z(Note2)
Hi-Z(Note2)
SSPCR0<SPO>
"High" state
"Low" state
MSB
MSB
MSB
MSB
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to 16bit
Capture data at the 2nd clock edge.
LSB
LSB
Capture data at the 1st clock edge.
LSB
LSB
Hi-Z(Note2)
SSPCR0<SPH>
Hi-Z(Note2
Hi-Z(Note1
MSB
MSB
TMPM362F10FG