TMPM362F10FG Toshiba, TMPM362F10FG Datasheet - Page 483

• Manufacturer Part Number: TMPM362F10FG
• Description: 32BIT MICROCONTROLLER
• Manufacturer: Toshiba
• Series: TX03r

Specifications of TMPM362F10FG

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 64MHz
• Connectivity: I²C, Microwire, SIO, SPI, SSP, UART/USART
• Peripherals: DMA, WDT
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 16x10b
• Package / Case: 144-LQFP
• Processor Series: TX03
• Core: ARM Cortex M3
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): 1024K
• Rom Type: Flash
• Ram (kbytes): 64K
• Number Of Pins: 144
• Package: LQFP(20x20)
• Vcc: 3V
• Cpu Mhz: 64
• Ssp (ch) Spi: 1
• I2c/sio (ch): 5
• Uart/sio (ch): 12
• Usb: -
• Can: -
• Ethernet: -
• External Bus Interface: Y
• Cs/wait Controller (ch): 4
• Dma Controller: 2
• 10-bit Da Converter: -
• 10-bit Ad Converter: 16
• 12-bit Ad Converter: -
• 16-bit Timer / Counter: 16
• Motor / Igbt Control: -
• Real Time Clock: 1
• Watchdog Timer: Y
• Osc Freq Detect: -
• Clock Gear: Y
• Low-power Hold Function: Y
• Remote Control Interface: Y
• Hardware Cec Controller: Y
• Comparators: -
• Low-voltage Detector: -
• Etm Hardware Trace: 4-bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Operating Temperature: -
• Number Of I /o: -
• Eeprom Size: -
• Oscillator Type: -
• Lead Free Status / Rohs Status: Details
• Other names: Q5704184A

14.5.2
14.5.3
14.5.4
14.5.5
one clock for acknowledgment signal. In slave mode, the clock for acknowledgement signals is counted. In
transmitter mode, the SBI releases the SDAx pin during clock cycle to receive acknowledgement signals
from the receiver. In receiver mode, the SBI pulls the SDAx pin to the "Low" level during the clock cycle
and generates acknowledgement signals. Also in slave mode, if a general-call address is received, the SBI
pulls the SDAx pin to the "Low" level during the clock cycle and generates acknowledgement signals.
SBI does not generate clock for acknowledgement signals. In slave mode, the clock for acknowledgement sig-
nals is counted.
ferred in a packet of eight bits. At other times, <BC[2:0]> keeps a previously programmed value.
and then the SBI recognizes a slave address transmitted by the master device and receives data in the address-
ing format.
mat. In the case of free data format, a slave address and a direction bit are not recognized; they are recog-
nized as data immediately after generation of the start condition.
the serial bus interface pins are at "High" level before setting <SBIM[1:0]> to "10". Also, ensure that the bus
is free before switching the operating mode to the port mode.
Setting SBIxCR1<ACK> to "1" selects the acknowledge mode.When operating as a master, the SBI adds
By setting <ACK> to "0", the non-acknowledgment mode is activated. When operating as a master, the
SBIxCR1<BC[2:0]> specifies the number of bits of the next data to be transmitted or received.
Under the start condition, <BC[2:0]> is set to "000", causing a slave address and the direction bit to be trans-
Setting "0" to SBIxI2CAR<ALS> and a slave address in SBIxI2CAR<SA[6:0]> sets addressing format,
If <ALS> is set to "1", the SBI does not recognize a slave address and receives data in the free data for-
The setting of SBIxCR2<SBIM[1:0]> controls the operating mode. To operate in I2C mode, ensure that
put to the "High" level. However, Master B still keeps the SCL bus line at the "Low" level, and Master
A stops counting of its "High" level period counting.After Master A detects that Master B brings its inter-
nal SCL output to the "High" level and brings the SCL bus line to the "High" level at the point c, it starts
counting of its "High" level period.
the SCL bus line becomes "Low".
the master with the longest "Low" level period among those connected to the bus.
Setting the Acknowledgement Mode
Setting the Number of Bits per Transfer
Slave Addressing and Address Recognition Mode
Operating mode
Master A completes counting of its "Low" level period at the point b, and brings its internal SCL out-
After that Master finishes counting the "High" level period, the Master pulls the SCL pin to "Low" and
This way, the clock on the bus is determined by the master with the shortest "High" level period and
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TMPM362F10FG