TMPM362F10FG Toshiba, TMPM362F10FG Datasheet - Page 627

• Manufacturer Part Number: TMPM362F10FG
• Description: 32BIT MICROCONTROLLER
• Manufacturer: Toshiba
• Series: TX03r

Specifications of TMPM362F10FG

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 64MHz
• Connectivity: I²C, Microwire, SIO, SPI, SSP, UART/USART
• Peripherals: DMA, WDT
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 16x10b
• Package / Case: 144-LQFP
• Processor Series: TX03
• Core: ARM Cortex M3
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): 1024K
• Rom Type: Flash
• Ram (kbytes): 64K
• Number Of Pins: 144
• Package: LQFP(20x20)
• Vcc: 3V
• Cpu Mhz: 64
• Ssp (ch) Spi: 1
• I2c/sio (ch): 5
• Uart/sio (ch): 12
• Usb: -
• Can: -
• Ethernet: -
• External Bus Interface: Y
• Cs/wait Controller (ch): 4
• Dma Controller: 2
• 10-bit Da Converter: -
• 10-bit Ad Converter: 16
• 12-bit Ad Converter: -
• 16-bit Timer / Counter: 16
• Motor / Igbt Control: -
• Real Time Clock: 1
• Watchdog Timer: Y
• Osc Freq Detect: -
• Clock Gear: Y
• Low-power Hold Function: Y
• Remote Control Interface: Y
• Hardware Cec Controller: Y
• Comparators: -
• Low-voltage Detector: -
• Etm Hardware Trace: 4-bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Operating Temperature: -
• Number Of I /o: -
• Eeprom Size: -
• Oscillator Type: -
• Lead Free Status / Rohs Status: Details
• Other names: Q5704184A

(2)
(3)
TADHP) is generated, and ADMOD2<EOCFHP> which indicates the completion of top-priority
AD conversion is set to "1".
When AD conversion is completed, ADMOD0<EOCFN> is set to "1". To confirm the completion
of AD conversion and to obtain the results, poll this bit.
"0" and <ADRxRF> = "1", a correct conversion result has been obtained.
After the AD conversion is completed, the top-priority AD conversion completion interrupt (IN-
AD conversion results are stored in the AD conversion result register SP.
To confirm the completion of AD conversion without using interrupts, data polling can be used.
AD conversion result storage register must be read by half word or word access. If <OVRx> =
Top-priority AD conversion completion
Data polling
・ Channel scan repeat conversion mode
rupt request INTAD is generated. ADMOD0<ADBFN> is not cleared to "0". It remains at
"1".
channel.
c. 8 conversions
Each time one AD conversion is completed, ADMOD0<EOCF> is set to "1" and inter-
AD conversion results are stored in a AD conversion result register corresponding to a
conversions are completed. In this case, the conversion results are sequentially stored
in the storage register ADREG08 through ADREG3B. After the conversion result is
stored in ADREG3B, <EOCFN> is set to "1", and the storage of subsequent conver-
sion results starts from ADREG08.
conversions are completed. In this case, the conversion results are sequentially stored
in the storage register ADREG08 through ADREG7F. After the conversion result is
stored in ADREG7F, <EOCFN> is set to "1", and the storage of subsequent conver-
sion results starts from ADREG08.
With <ITM[1:0]> set to "01", an interrupt request is generated each time four AD
With <ITM[1:0]> set to "10", an interrupt request is generated each time eight AD
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TMPM362F10FG