TMPM362F10FG Toshiba, TMPM362F10FG Datasheet - Page 596

• Manufacturer Part Number: TMPM362F10FG
• Description: 32BIT MICROCONTROLLER
• Manufacturer: Toshiba
• Series: TX03r

Specifications of TMPM362F10FG

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 64MHz
• Connectivity: I²C, Microwire, SIO, SPI, SSP, UART/USART
• Peripherals: DMA, WDT
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 16x10b
• Package / Case: 144-LQFP
• Processor Series: TX03
• Core: ARM Cortex M3
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): 1024K
• Rom Type: Flash
• Ram (kbytes): 64K
• Number Of Pins: 144
• Package: LQFP(20x20)
• Vcc: 3V
• Cpu Mhz: 64
• Ssp (ch) Spi: 1
• I2c/sio (ch): 5
• Uart/sio (ch): 12
• Usb: -
• Can: -
• Ethernet: -
• External Bus Interface: Y
• Cs/wait Controller (ch): 4
• Dma Controller: 2
• 10-bit Da Converter: -
• 10-bit Ad Converter: 16
• 12-bit Ad Converter: -
• 16-bit Timer / Counter: 16
• Motor / Igbt Control: -
• Real Time Clock: 1
• Watchdog Timer: Y
• Osc Freq Detect: -
• Clock Gear: Y
• Low-power Hold Function: Y
• Remote Control Interface: Y
• Hardware Cec Controller: Y
• Comparators: -
• Low-voltage Detector: -
• Etm Hardware Trace: 4-bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Operating Temperature: -
• Number Of I /o: -
• Eeprom Size: -
• Oscillator Type: -
• Lead Free Status / Rohs Status: Details
• Other names: Q5704184A

19.3
BACKUP Mode Operation
(2)
(3)
Transition to BACKUP mode
Returning from backup mode (Releasing)
1. Setting modes and clearing release source of BACKUP mode
2. Transition to the BACKUP mode
1. Releasing source of BACKUP mode
2. Releasing operation by external RESET input
3. Releasing operation by releasing source of BACKUP mode
SLEEP mode.
tion" and "Warm reset operation".
ted register of R
TC if BACKUP mode is cleared by external reset input.
down block. Depending on the returned modes, high-speed oscillator and low-speed oscilla-
tor will start operation.
time, internal reset signal of power shut down block which returned from BACKUP mode
is continuing active level. Internal reset is cleared after warm up time has elapsed, and
then MCU returns to the preceding mode of BACKUP mode.
By the CGSTBYCR<STBY> register, set to the BACKUP STOP mode or BACKUP
Clear the interrupt which releases from BACKUP mode, then execute WFI instruction
Releasing source of BACKUP STOP and BACKUP SLEEP shown as below.
BACKUP releasing operation by external reset input is referred to "Cold reset opera-
Note that it is not guaranteed the contents of BACKUP RAM and clock / calendar rela-
If the event of releasing source are received, regulator starts to supply power to the shut
The warm up timer will starts when the oscillation becomes stable. During warm up
Precaution after BACKUP mode released
・ By reading CGRSTFLG register, it can be found which reset are occurred.
・ Make sure to perform the port A, B, C, D, E, F, G, H, K, O and P setting before releasing port
Precautions for the use of the BACKUP mode (about debug tool)
The communication with debug tool is disconnected, if MCU changes to the BACKUP mode. In
this case, it is necessary to reconnect to debug tool.
keep function by (CGSTBYCR<PTKEEP>="0").
BACKUP SLEEP
BACKUP STOP
BACKUP mode
External RESET input, INT0 to 4,8,E,F, INTKWUP (Static)
External RESET input, INT0 to 4,8,E,F, INTKWUP (Dynamic / Static),
INTRTC, INTCECRX, INTRMCRX0, INTRMCRX1
Page 572
Releasing source of BACKUP mode
TMPM362F10FG