TMPM362F10FG Toshiba, TMPM362F10FG Datasheet - Page 437

• Manufacturer Part Number: TMPM362F10FG
• Description: 32BIT MICROCONTROLLER
• Manufacturer: Toshiba
• Series: TX03r

Specifications of TMPM362F10FG

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 64MHz
• Connectivity: I²C, Microwire, SIO, SPI, SSP, UART/USART
• Peripherals: DMA, WDT
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 16x10b
• Package / Case: 144-LQFP
• Processor Series: TX03
• Core: ARM Cortex M3
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): 1024K
• Rom Type: Flash
• Ram (kbytes): 64K
• Number Of Pins: 144
• Package: LQFP(20x20)
• Vcc: 3V
• Cpu Mhz: 64
• Ssp (ch) Spi: 1
• I2c/sio (ch): 5
• Uart/sio (ch): 12
• Usb: -
• Can: -
• Ethernet: -
• External Bus Interface: Y
• Cs/wait Controller (ch): 4
• Dma Controller: 2
• 10-bit Da Converter: -
• 10-bit Ad Converter: 16
• 12-bit Ad Converter: -
• 16-bit Timer / Counter: 16
• Motor / Igbt Control: -
• Real Time Clock: 1
• Watchdog Timer: Y
• Osc Freq Detect: -
• Clock Gear: Y
• Low-power Hold Function: Y
• Remote Control Interface: Y
• Hardware Cec Controller: Y
• Comparators: -
• Low-voltage Detector: -
• Etm Hardware Trace: 4-bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Operating Temperature: -
• Number Of I /o: -
• Eeprom Size: -
• Oscillator Type: -
• Lead Free Status / Rohs Status: Details
• Other names: Q5704184A

12.16.1.2
(1)
Receive
The SCLK output can be started by setting the receive enable bit SCxMOD0<RXE> to "1".
SCLK Output Mode
・ If double buffer is disabled (SCxMOD2<WBUF> = "0")
・ If double buffer is enabled (SCxMOD2<WBUF> = "1")
ister each time the CPU reads received data. When all the 8 bits are received, the INTRXx
interrupt is generated.
receive the next frame. A data is moved from the shift register to the receive buffer, the re-
ceive buffer full flag SCxMOD2<RBFLL> is set to "1" and the INTRXx is generated.
fore completing reception of the next 8 bits, the INTRXx interrupt is not generated and the
SCLK output stops. In this state, reading data from the receive buffer allows data in the
shift register to move to the receive buffer and thus the INTRXx interrupt is generated and
data reception resumes.
A clock pulse is outputted from the SCLK pin and the next data is stored into the shift reg-
Data stored in the shift register is moved to the receive buffer and the receive buffer can
While data is in the receive buffer, if the data cannot be read from the receive buffer be-
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TMPM362F10FG