TMPM362F10FG Toshiba, TMPM362F10FG Datasheet - Page 519

• Manufacturer Part Number: TMPM362F10FG
• Description: 32BIT MICROCONTROLLER
• Manufacturer: Toshiba
• Series: TX03r

Specifications of TMPM362F10FG

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 64MHz
• Connectivity: I²C, Microwire, SIO, SPI, SSP, UART/USART
• Peripherals: DMA, WDT
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 16x10b
• Package / Case: 144-LQFP
• Processor Series: TX03
• Core: ARM Cortex M3
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): 1024K
• Rom Type: Flash
• Ram (kbytes): 64K
• Number Of Pins: 144
• Package: LQFP(20x20)
• Vcc: 3V
• Cpu Mhz: 64
• Ssp (ch) Spi: 1
• I2c/sio (ch): 5
• Uart/sio (ch): 12
• Usb: -
• Can: -
• Ethernet: -
• External Bus Interface: Y
• Cs/wait Controller (ch): 4
• Dma Controller: 2
• 10-bit Da Converter: -
• 10-bit Ad Converter: 16
• 12-bit Ad Converter: -
• 16-bit Timer / Counter: 16
• Motor / Igbt Control: -
• Real Time Clock: 1
• Watchdog Timer: Y
• Osc Freq Detect: -
• Clock Gear: Y
• Low-power Hold Function: Y
• Remote Control Interface: Y
• Hardware Cec Controller: Y
• Comparators: -
• Low-voltage Detector: -
• Etm Hardware Trace: 4-bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Operating Temperature: -
• Number Of I /o: -
• Eeprom Size: -
• Oscillator Type: -
• Lead Free Status / Rohs Status: Details
• Other names: Q5704184A

15.3.7
31-25
24
23-22
21-20
19
18-16
15
14-12
11
bit symbol
After reset
bit symbol
After reset
bit symbol
After reset
bit symbol
After reset
Bit
−
CECACKDIS
−
CECHNC[1:0]
−
CECLNC[2:0]
−
CECMIN[2:0]
−
Bit Symbol
CECRCR1 (Receive Control Register 1)
31
23
15
0
0
0
7
0
-
-
-
-
R
R/W
R
R/W
R
R/W
R
R/W
R
Type
30
22
14
0
0
0
6
0
-
-
Read as 0.
Logical "0" as ACK response
0: send
1: not send
Specifies if logical "0" is sent or not as an ACK response to the data block when destination address
corresponds with the address set in the logical address register.
(Logical "0" is sent to the header block as an ACK response regardless of the bit setting when detecting the
addresses corresponding)
Read as 0.
The number of "High" samplings for noise cancellation.
Specifies the time of the noise cancellation for each 1/fs when detecting "High".
It is considered as noise if "High"s of the same number as the specified cycles are not sampled.
Read as 0.
The number of "Low" samplings for noise cancellation.
Specifies the time of the noise cancellation for each 1/fs when detecting "Low".
It is considered as noise if "Low"s of the same number as the specified cycles are not sampled.
Read as 0.
Time to identify as minimum cycle error
Specifies the minimum time to identify a valid bit.
Base time is 67/fs (approx.2.045) ms. Enables to specify it between the ranges −4/fs to +3/fs by the unit
of 1/fs.
An interrupt is generated and "Low" is output to CEC for approx. 3.63 ms when one bit cycle is shorter
than the
specified time.
Read as 0.
000:
001:
010:
011:
000:
001:
010:
011:
00:
01:
10:
11:
None
1/fs
2/fs
3/fs
None (one time of fs clock observed.)
1/fs (two consecutive fs clocks observed)
2/fs (three consecutive fs clocks observed)
3/fs (four consecutive fs clocks observed.)
67/fs (approx.2.045ms)
67/fs + 1/fs
67/fs + 2/fs
67/fs + 3/fs
CECDAT
CECMIN
29
21
13
0
0
0
5
0
-
(one time of fs clock observed.)
(two consecutive fs clocks observed.)
(three consecutive fs clocks observed.)
(four consecutive fs clocks observed.)
CECHNC
Page 495
28
20
12
0
0
0
4
0
-
27
19
11
Function
0
0
0
3
0
-
-
-
CECTOUT
100:
101:
110:
111:
100:
101:
110:
111:
− (Reserved)
− (Reserved)
− (Reserved)
− (Reserved)
67/fs − 1/fs
67/fs − 2/fs
67/fs − 3/fs
67/fs − 4/fs
26
18
10
0
0
0
2
0
-
CECRIHLD
CECMAX
CECLNC
25
17
0
0
9
0
1
0
-
TMPM362F10FG
CECACKDIS
CECOTH
24
16
0
0
8
0
0
0