TMPM362F10FG Toshiba, TMPM362F10FG Datasheet - Page 418
TMPM362F10FG
Manufacturer Part Number
TMPM362F10FG
Description
32BIT MICROCONTROLLER
Manufacturer
Toshiba
Series
TX03r
Datasheet
1.TMPM362F10FG.pdf
(744 pages)
Specifications of TMPM362F10FG
Core Processor
ARM® Cortex-M3™
Core Size
32-Bit
Speed
64MHz
Connectivity
I²C, Microwire, SIO, SPI, SSP, UART/USART
Peripherals
DMA, WDT
Program Memory Size
1MB (1M x 8)
Program Memory Type
FLASH
Ram Size
64K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 16x10b
Package / Case
144-LQFP
Processor Series
TX03
Core
ARM Cortex M3
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2
Product Summaries
Summary
Lead Free
Yes
Rohs Compatible Product(s)
Available
Rom (kbytes)
1024K
Rom Type
Flash
Ram (kbytes)
64K
Number Of Pins
144
Package
LQFP(20x20)
Vcc
3V
Cpu Mhz
64
Ssp (ch) Spi
1
I2c/sio (ch)
5
Uart/sio (ch)
12
Usb
-
Can
-
Ethernet
-
External Bus Interface
Y
Cs/wait Controller (ch)
4
Dma Controller
2
10-bit Da Converter
-
10-bit Ad Converter
16
12-bit Ad Converter
-
16-bit Timer / Counter
16
Motor / Igbt Control
-
Real Time Clock
1
Watchdog Timer
Y
Osc Freq Detect
-
Clock Gear
Y
Low-power Hold Function
Y
Remote Control Interface
Y
Hardware Cec Controller
Y
Comparators
-
Low-voltage Detector
-
Etm Hardware Trace
4-bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Operating Temperature
-
Number Of I /o
-
Eeprom Size
-
Oscillator Type
-
Lead Free Status / Rohs Status
Details
Other names
Q5704184A
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
TMPM362F10FG
Manufacturer:
Freescale
Quantity:
488
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12.9
Status Flag
12.9
12.10
12.10.1
moved from the receive shift register to the receive buffers, this bit changes to "1" while reading this bit changes
it to "0".
mit shift register, this bit is set to "1" When data is set to the transmit buffers, the bit is cleared to "0".
modes. The table below shows the meaning in each mode.
The SCxMOD2 register has two types of flag. This bit is significant only when the double buffer is enabled.
<RBFLL> is a flag to show that the receive buffer is full. When one frame of data is received and the data is
<TBEMP> shows that the transmit buffers are empty. When data in the transmit buffers is moved to the trans-
Three error flags are provided in the SCxCR register. The meaning of the flags is changed depending on the
These flags are cleared to "0" after reading the SCxCR register.
Status Flag
ception of the next frame of receive data before the receive buffer has been read. If the receive FIFO is ena-
bled, the received data is automatically moved to the receive FIFO and no overrun error will be generated un-
til the receive FIFO is full (or until the usable bytes are fully occupied).
Error Flag
Table 12-12 shows correction between modes and FIFO.
In both UART and I/O interface modes, this bit is set to "1" when an error is generated by completing the re-
In the I/O interface with SCLK output mode, the SCLK output stops upon setting the flag.
Note:To use TX/RX FIFO buffer, TX/RX FIFO must be cleared after setting the SIO transfer mode
OERR Flag
(SCLK output)
(SCLK input)
I/O interface
I/O interface
(half duplex/ full duplex) and enabling FIFO (SCxFCNF<CNFG> = "1").
UART
Mode
Table 12-12 Mode and FIFO Composition
Half duplex RX
Half duplex TX
Full duplex
Overrun error
Overrun error
Undefined
<OERR>
SCxMOD1<FDPX[1:0]>
"01"
"10"
"11"
Page 394
(When a double buffer and
(When using double buffer
Underrun error
FIFO unused)
Fixed to "0"
Parity error
Undefined
<PERR>
or FIFO)
RX FIFO
Flag
4byte
2byte
-
TX FIFO
4byte
2byte
-
Framing error
Fixed to "0"
Fixed to "0"
<FERR>
TMPM362F10FG
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