TMPM362F10FG Toshiba, TMPM362F10FG Datasheet - Page 541

• Manufacturer Part Number: TMPM362F10FG
• Description: 32BIT MICROCONTROLLER
• Manufacturer: Toshiba
• Series: TX03r

Specifications of TMPM362F10FG

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 64MHz
• Connectivity: I²C, Microwire, SIO, SPI, SSP, UART/USART
• Peripherals: DMA, WDT
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 16x10b
• Package / Case: 144-LQFP
• Processor Series: TX03
• Core: ARM Cortex M3
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): 1024K
• Rom Type: Flash
• Ram (kbytes): 64K
• Number Of Pins: 144
• Package: LQFP(20x20)
• Vcc: 3V
• Cpu Mhz: 64
• Ssp (ch) Spi: 1
• I2c/sio (ch): 5
• Uart/sio (ch): 12
• Usb: -
• Can: -
• Ethernet: -
• External Bus Interface: Y
• Cs/wait Controller (ch): 4
• Dma Controller: 2
• 10-bit Da Converter: -
• 10-bit Ad Converter: 16
• 12-bit Ad Converter: -
• 16-bit Timer / Counter: 16
• Motor / Igbt Control: -
• Real Time Clock: 1
• Watchdog Timer: Y
• Osc Freq Detect: -
• Clock Gear: Y
• Low-power Hold Function: Y
• Remote Control Interface: Y
• Hardware Cec Controller: Y
• Comparators: -
• Low-voltage Detector: -
• Etm Hardware Trace: 4-bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Operating Temperature: -
• Number Of I /o: -
• Eeprom Size: -
• Oscillator Type: -
• Lead Free Status / Rohs Status: Details
• Other names: Q5704184A

15.4.3
15.4.3.1
Wait for bus
to be free
ing edge signal does not exit for specified bit cycles, and then sends a start bit. The confirmation of bus
free wait is performed all the time. Thus once bus free wait condition is satisfied, a transmission will
start soon when transmission setting is done.
buffer to the shift register. When the transmission of the first bit of the one byte data begins, transmission
interrupt is generates, and CECTSTAT<CECTISTA> is set. After transmission interrupt generation, next
one byte data is prepared to the transmit data buffer.
sion and ACK bit response confirmation.
ACK bit transmission and ACK bit response. By the end of transmission interrupt generates, CECT-
STAT<CECTIEND> is set.
Transmission
In the transmission setting, the CEC firstly confirms the bus free wait status; it checks whether a CEC fall-
After transmitting a start bit, CEC transmits one byte data and EOM data that are stored in the transmit
One byte data transmission completes in order of transmission of 8 bits data, EOM bit, ACK bit transmis-
Data transmission continues until EOM is set to "1".
If EOM is set to "1", the end of transmission interrupt generates after confirmation of data, EOM,
Interrupt generation ends a series of transmission process, and CECTEN<CECTEN> is cleared.
If an error is generated during transmission, an error interrupt is generates to stop transmission.
Even if reception is enabled, no reception is executed during transmission.
Basic Operation
S
H
D1
D2
(beginning of transmission)
Transmit interrupt
D3
Page 517
D4
Dn-2
(end of transmission)
Transmit interrupt
Dn-1
TMPM362F10FG
Dn