TMPM362F10FG Toshiba, TMPM362F10FG Datasheet - Page 87

• Manufacturer Part Number: TMPM362F10FG
• Description: 32BIT MICROCONTROLLER
• Manufacturer: Toshiba
• Series: TX03r

Specifications of TMPM362F10FG

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 64MHz
• Connectivity: I²C, Microwire, SIO, SPI, SSP, UART/USART
• Peripherals: DMA, WDT
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 16x10b
• Package / Case: 144-LQFP
• Processor Series: TX03
• Core: ARM Cortex M3
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): 1024K
• Rom Type: Flash
• Ram (kbytes): 64K
• Number Of Pins: 144
• Package: LQFP(20x20)
• Vcc: 3V
• Cpu Mhz: 64
• Ssp (ch) Spi: 1
• I2c/sio (ch): 5
• Uart/sio (ch): 12
• Usb: -
• Can: -
• Ethernet: -
• External Bus Interface: Y
• Cs/wait Controller (ch): 4
• Dma Controller: 2
• 10-bit Da Converter: -
• 10-bit Ad Converter: 16
• 12-bit Ad Converter: -
• 16-bit Timer / Counter: 16
• Motor / Igbt Control: -
• Real Time Clock: 1
• Watchdog Timer: Y
• Osc Freq Detect: -
• Clock Gear: Y
• Low-power Hold Function: Y
• Remote Control Interface: Y
• Hardware Cec Controller: Y
• Comparators: -
• Low-voltage Detector: -
• Etm Hardware Trace: 4-bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Operating Temperature: -
• Number Of I /o: -
• Eeprom Size: -
• Oscillator Type: -
• Lead Free Status / Rohs Status: Details
• Other names: Q5704184A

7.1.2.1
Table 7-1 Exception Types and Priority
7~10
16~
No.
11
12
13
14
15
1
2
3
4
5
6
(1)
(2)
Exception Request and Detection
Reset
Non-Maskable Interrupt
Hard Fault
Memory Management
Bus Fault
Usage Fault
Reserved
SVCall
Debug Monitor
Reserved
PendSV
SysTick
External interrupt
quests from external interrupt pins or peripheral functions.
ror condition occurs during instruction execution.
cess violation to the Fault region.
rupts that are used for releasing a standby mode, relevant settings must be made in the clock genera-
tor. For details, refer to "7.5 Interrupts".
el to that exception. Memory Management, Bus Fault and Usage Fault exceptions can be enabled or
disabled. If a disabled exception occurs, it is handled as Hard Fault.
Note 1: This product does not contain the MPU.
Note 2: External interrupts have different sources and numbers in each product. For details,
Exception sources include instruction execution by the CPU, memory accesses, and interrupt re-
An exception occurs when the CPU executes an instruction that causes an exception or when an er-
An exception also occurs by an instruction fetch from the Execute Never (XN) region or an ac-
An interrupt request is generated from an external interrupt pin or peripheral function.For inter-
If multiple exceptions occur simultaneously, the CPU takes the exception with the highest priority.
Table 7-1 shows the priority of exceptions. "Configurable" means that you can assign a priority lev-
Exception occurrence
Exception detection
Exception type
see"7.5.1.5 List of Interrupt Sources".
−3 (highest)
−2
−1
Configurable
Configurable
Configurable
−
Configurable
Configurable
−
Configurable
Configurable
Configurable
Priority
Reset pin, WDT or SYSRETREQ
NMI pin or WDT
Fault that cannot activate because a higher-priority fault is being han-
dled or it is disabled
Exception from the Memory Protection Unit (MPU) (Note 1)
Instruction fetch from the Execute Never (XN) region
Access violation to the Hard Fault region of the memory map
Undefined instruction execution or other faults related to instruction ex-
ecution
System service call with SVC instruction
Debug monitor when the CPU is not faulting
Pendable system service request
Notification from system timer
External interrupt pin or peripheral function (Note2)
Page 63
Description
TMPM362F10FG