TMPM362F10FG Toshiba, TMPM362F10FG Datasheet - Page 484

• Manufacturer Part Number: TMPM362F10FG
• Description: 32BIT MICROCONTROLLER
• Manufacturer: Toshiba
• Series: TX03r

Specifications of TMPM362F10FG

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 64MHz
• Connectivity: I²C, Microwire, SIO, SPI, SSP, UART/USART
• Peripherals: DMA, WDT
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 16x10b
• Package / Case: 144-LQFP
• Processor Series: TX03
• Core: ARM Cortex M3
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): 1024K
• Rom Type: Flash
• Ram (kbytes): 64K
• Number Of Pins: 144
• Package: LQFP(20x20)
• Vcc: 3V
• Cpu Mhz: 64
• Ssp (ch) Spi: 1
• I2c/sio (ch): 5
• Uart/sio (ch): 12
• Usb: -
• Can: -
• Ethernet: -
• External Bus Interface: Y
• Cs/wait Controller (ch): 4
• Dma Controller: 2
• 10-bit Da Converter: -
• 10-bit Ad Converter: 16
• 12-bit Ad Converter: -
• 16-bit Timer / Counter: 16
• Motor / Igbt Control: -
• Real Time Clock: 1
• Watchdog Timer: Y
• Osc Freq Detect: -
• Clock Gear: Y
• Low-power Hold Function: Y
• Remote Control Interface: Y
• Hardware Cec Controller: Y
• Comparators: -
• Low-voltage Detector: -
• Etm Hardware Trace: 4-bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Operating Temperature: -
• Number Of I /o: -
• Eeprom Size: -
• Oscillator Type: -
• Lead Free Status / Rohs Status: Details
• Other names: Q5704184A

14.5
Control in the I2C Bus Mode
14.5.6
14.5.7
14.5.8
SCLx pin
SDAx pin
SBI as a receiver.
<TRX> is set to "0".
mitted, <TRX> is set to "0" by the hardware. If the direction bit is "0", <TRX> changes to "1". If the SBI
does not receive acknowledgement, <TRX> retains the previous value.
lost.
when it detects the stop condition on the bus or the arbitration lost.
quence for generating the start condition and to output the slave address and the direction bit prospectively writ-
ten in the data buffer register. <ACK> must be set to "1" in advance.
for generating the stop condition on the bus. The contents of <MST, TRX, BB, PIN> should not be altered un-
til the stop condition appears on the bus.
Setting SBIxCR2<TRX> to "1" configures the SBI as a transmitter. Setting <TRX> to "0" configures the
At the slave mode:
If the value of the direction bit (R/W) is "1", <TRX> is set to "1" by the hardware. If the bit is "0",
As a master device, the SBI receives acknowledgement from a slave device. If the direction bit of "1" is trans-
<TRX> is cleared to "0" by the hardware when it detects the stop condition on the bus or the arbitration
If SBI is used in free data format, <TRX> is not changed by the hardware.
Setting SBIxCR2<MST> to "1" configures the SBI to operate as a master device.
Setting <MST> to "0" configures the SBI as a slave device. <MST> is cleared to "0" by the hardware
When SBIxSR<BB> is "0", writing "1" to SBIxCR2<MST, TRX, BB, PIN> causes the SBI to start a se-
When <BB> is "1", writing "1" to <MST, TRX, PIN> and "0" to <BB> causes the SBI to start a sequence
Configuring the SBI as a Transmitter or a Receiver
Configuring the SBI as a Master or a Slave
Generating Start and Stop Conditions
・ when data is transmitted in the addressing format.
・ when the received slave address matches the value specified at SBIxI2CAR.
・ when a general-call address is received; i.e., the eight bits following the start condition are all zeros.
Start condition
Figure 14-5 Generating the Start Condition and a Slave Address
A6
1
A5
2
A4
Slave address and direction bit
3
Page 460
A3
4
A2
5
A1
6
A0
7
R/W
8
Acknowledgement signal
TMPM362F10FG
9