TMPM362F10FG Toshiba, TMPM362F10FG Datasheet - Page 591
TMPM362F10FG
Manufacturer Part Number
TMPM362F10FG
Description
32BIT MICROCONTROLLER
Manufacturer
Toshiba
Series
TX03r
Datasheet
1.TMPM362F10FG.pdf
(744 pages)
Specifications of TMPM362F10FG
Core Processor
ARM® Cortex-M3™
Core Size
32-Bit
Speed
64MHz
Connectivity
I²C, Microwire, SIO, SPI, SSP, UART/USART
Peripherals
DMA, WDT
Program Memory Size
1MB (1M x 8)
Program Memory Type
FLASH
Ram Size
64K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 16x10b
Package / Case
144-LQFP
Processor Series
TX03
Core
ARM Cortex M3
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2
Product Summaries
Summary
Lead Free
Yes
Rohs Compatible Product(s)
Available
Rom (kbytes)
1024K
Rom Type
Flash
Ram (kbytes)
64K
Number Of Pins
144
Package
LQFP(20x20)
Vcc
3V
Cpu Mhz
64
Ssp (ch) Spi
1
I2c/sio (ch)
5
Uart/sio (ch)
12
Usb
-
Can
-
Ethernet
-
External Bus Interface
Y
Cs/wait Controller (ch)
4
Dma Controller
2
10-bit Da Converter
-
10-bit Ad Converter
16
12-bit Ad Converter
-
16-bit Timer / Counter
16
Motor / Igbt Control
-
Real Time Clock
1
Watchdog Timer
Y
Osc Freq Detect
-
Clock Gear
Y
Low-power Hold Function
Y
Remote Control Interface
Y
Hardware Cec Controller
Y
Comparators
-
Low-voltage Detector
-
Etm Hardware Trace
4-bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Operating Temperature
-
Number Of I /o
-
Eeprom Size
-
Oscillator Type
-
Lead Free Status / Rohs Status
Details
Other names
Q5704184A
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
TMPM362F10FG
Manufacturer:
Freescale
Quantity:
488
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18.6
KEY input
The timing of interrupt
Result of an internal sampling
KWUP input Detection Timing
1. PJPUP<PJnUP>="1", KWUPCRn<DPEn>="0" with always pull-up
2. PJPUP<PJnUP>="1", KWUPCRn<DPEn>="1" with dynamic pull-up
edges by setting KWUPCRn<KEYn>. The active state of key inputs are continuously detected.
before fs at the end of the T1 period. Therefore, a key input not shorter than the T2 period is nee-
ded.There is a delay up to the T2 period before key input detection. The figure below shows an example
of defining the active state to the falling edge.
The active state of each key input can be defined to the high or low level or to the rising or falling
Detection of the active state of each key input (interrupt detection) is carried out at the edge one-clock
Pull-up (period of T1)
High or Hi-Z
Cycle (period of T2)
Need more than T2 period (Low period)
Page 567
KEY input Detection
High or Hi-Z or Low
TMPM362F10FG
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