TMPM362F10FG Toshiba, TMPM362F10FG Datasheet - Page 494
TMPM362F10FG
Manufacturer Part Number
TMPM362F10FG
Description
32BIT MICROCONTROLLER
Manufacturer
Toshiba
Series
TX03r
Datasheet
1.TMPM362F10FG.pdf
(744 pages)
Specifications of TMPM362F10FG
Core Processor
ARM® Cortex-M3™
Core Size
32-Bit
Speed
64MHz
Connectivity
I²C, Microwire, SIO, SPI, SSP, UART/USART
Peripherals
DMA, WDT
Program Memory Size
1MB (1M x 8)
Program Memory Type
FLASH
Ram Size
64K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 16x10b
Package / Case
144-LQFP
Processor Series
TX03
Core
ARM Cortex M3
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2
Product Summaries
Summary
Lead Free
Yes
Rohs Compatible Product(s)
Available
Rom (kbytes)
1024K
Rom Type
Flash
Ram (kbytes)
64K
Number Of Pins
144
Package
LQFP(20x20)
Vcc
3V
Cpu Mhz
64
Ssp (ch) Spi
1
I2c/sio (ch)
5
Uart/sio (ch)
12
Usb
-
Can
-
Ethernet
-
External Bus Interface
Y
Cs/wait Controller (ch)
4
Dma Controller
2
10-bit Da Converter
-
10-bit Ad Converter
16
12-bit Ad Converter
-
16-bit Timer / Counter
16
Motor / Igbt Control
-
Real Time Clock
1
Watchdog Timer
Y
Osc Freq Detect
-
Clock Gear
Y
Low-power Hold Function
Y
Remote Control Interface
Y
Hardware Cec Controller
Y
Comparators
-
Low-voltage Detector
-
Etm Hardware Trace
4-bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Operating Temperature
-
Number Of I /o
-
Eeprom Size
-
Oscillator Type
-
Lead Free Status / Rohs Status
Details
Other names
Q5704184A
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
TMPM362F10FG
Manufacturer:
Freescale
Quantity:
488
- Current page: 494 of 744
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14.6
Data Transfer Procedure in the I2C Bus ModeI2C
14.6.3.2
INTSBIx interrupt
if TRX = 0
Then go to other processing.
if AL = 0
Then go to other processing.
if AAS = 0
Then go to other processing.
SBIxCR1
SBIxDBR
rupt request is generated, <PIN> is cleared to "0", and the SCL pin is pulled to the "Low" level.
ter a period of t
is carried out.
in the slave receiver mode.
In the slave mode, the SBI generates the INTSBIx interrupt request on four occasions:
1) when the SBI has received any slave address from the master.
2) when the SBI has received a general-call address.
3) when the received slave address matches its address.
4) when a data transfer has been completed in response to a general-call.
Also, if the SBI detects Arbitration Lost in the master mode, it switches to the slave mode.
Upon the completion of data word transfer in which Arbitration Lost is detected, the INTSBIx inter-
When data is written to or read from SBIxDBR or when <PIN> is set to "1", the SCLx pin is released af-
In the slave mode, the normal slave mode processing or the processing as a result of Arbitration Lost
SBIxSR<AL>, <TRX>, <AAS> and <AD0> are tested to determine the processing required.
"Table 14-2 Processing in Slave Mode"shows the slave mode states and required processing.
Example: When the received slave address matches the SBI's own address and the direction bit is "1"
Note:X; Don’t care
Slave mode (<MST> = "0")
←
←
X
X
LOW
X
X
.
X
X
1
X
0
0
X
X
X
X
Page 470
X
X
Sets the number of bits to be transmitted.
Sets the transmit data.
TMPM362F10FG
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