TMPM362F10FG Toshiba, TMPM362F10FG Datasheet - Page 489
TMPM362F10FG
Manufacturer Part Number
TMPM362F10FG
Description
32BIT MICROCONTROLLER
Manufacturer
Toshiba
Series
TX03r
Datasheet
1.TMPM362F10FG.pdf
(744 pages)
Specifications of TMPM362F10FG
Core Processor
ARM® Cortex-M3™
Core Size
32-Bit
Speed
64MHz
Connectivity
I²C, Microwire, SIO, SPI, SSP, UART/USART
Peripherals
DMA, WDT
Program Memory Size
1MB (1M x 8)
Program Memory Type
FLASH
Ram Size
64K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 16x10b
Package / Case
144-LQFP
Processor Series
TX03
Core
ARM Cortex M3
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2
Product Summaries
Summary
Lead Free
Yes
Rohs Compatible Product(s)
Available
Rom (kbytes)
1024K
Rom Type
Flash
Ram (kbytes)
64K
Number Of Pins
144
Package
LQFP(20x20)
Vcc
3V
Cpu Mhz
64
Ssp (ch) Spi
1
I2c/sio (ch)
5
Uart/sio (ch)
12
Usb
-
Can
-
Ethernet
-
External Bus Interface
Y
Cs/wait Controller (ch)
4
Dma Controller
2
10-bit Da Converter
-
10-bit Ad Converter
16
12-bit Ad Converter
-
16-bit Timer / Counter
16
Motor / Igbt Control
-
Real Time Clock
1
Watchdog Timer
Y
Osc Freq Detect
-
Clock Gear
Y
Low-power Hold Function
Y
Remote Control Interface
Y
Hardware Cec Controller
Y
Comparators
-
Low-voltage Detector
-
Etm Hardware Trace
4-bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Operating Temperature
-
Number Of I /o
-
Eeprom Size
-
Oscillator Type
-
Lead Free Status / Rohs Status
Details
Other names
Q5704184A
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
TMPM362F10FG
Manufacturer:
Freescale
Quantity:
488
- Current page: 489 of 744
- Download datasheet (8Mb)
14.6
14.6.1
14.6.2
14.6.2.1
SBIxCR1
SBIxI2CAR
SBIxCR2
Data Transfer Procedure in the I2C Bus ModeI2C
at <ALS>. (<ALS> must be cleared to "0" when using the addressing format).
"High" first. Then write "0" to SBIxCR2<MST, TRX, BB>, "1" to <PIN>, "10" to <SBIM[1:0]> and "0" to
the bit 1 and 0.
First, program SBIxCR1<ACK, SCK[2:0]>. Writing "000" to SBIxCR1<BC[2:0]> at the time.
Next, program SBIxI2CAR by specifying a slave address at <SA[6:0]> and an address recognition mode
To configure the Serial Bus Interface as a slave receiver, ensure that the serial bus interface pin is at
edgment mode. Write to SBIxDBR a slave address and a direction bit to be transmitted.
on the bus. Following the start condition, the SBI generates nine clocks from the SCL pin. The SBI out-
puts the slave address and the direction bit specified at SBIxDBR with the first eight clocks, and releases
the SDA line in the ninth clock to receive an acknowledgment signal from the slave device.
"0". In the master mode, the SBI holds the SCL line at the "Low" level while <PIN> is = "0".<TRX>
changes its value according to the transmitted direction bit at generation of the INTSBIx interrupt re-
quest, provided that an acknowledgment signal has been returned from the slave device.
Device Initialization
Generating the Start Condition and a Slave Address
Note:Initialization of the serial bus interface circuit must be completed within a period that any device
Note:X; Don’t care
In the master mode, the following steps are required to generate the start condition and a slave address.
First, ensure that the bus is free (<BB> = "0"). Then, write "1" to SBIxCR1<ACK> to select the acknowl-
When <BB> = "0", writing "1111" to SBIxCR2<MST, TRX, BB, PIN> generates the start condition
The INTSBIx interrupt request is generated on the falling of the ninth clock, and <PIN> is cleared to
Note:To output salve address, check with software that the bus is free before writing to SBIxDBR. If this
Master mode
←
←
←
does not generate start condition after all devices connected to the bus were initialized. If this rule is
not followed, data may not be received correctly because other devices may start transfer before the
initialization of the serial bus interface circuit is completed.
rule is not followed, data being output on the bus may get ruined.
7
0
X
0
6
0
X
0
5
0
X
0
4
X
X
1
3
0
X
1
2
X
X
0
1
X
X
0
0
X
X
0
Page 465
Specifies ACK and SCL clock.
Specifies a slave address and an address recognition mode.
Configures the SBI as a slave receiver.
TMPM362F10FG
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