TMPM362F10FG Toshiba, TMPM362F10FG Datasheet - Page 102

• Manufacturer Part Number: TMPM362F10FG
• Description: 32BIT MICROCONTROLLER
• Manufacturer: Toshiba
• Series: TX03r

Specifications of TMPM362F10FG

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 64MHz
• Connectivity: I²C, Microwire, SIO, SPI, SSP, UART/USART
• Peripherals: DMA, WDT
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 16x10b
• Package / Case: 144-LQFP
• Processor Series: TX03
• Core: ARM Cortex M3
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): 1024K
• Rom Type: Flash
• Ram (kbytes): 64K
• Number Of Pins: 144
• Package: LQFP(20x20)
• Vcc: 3V
• Cpu Mhz: 64
• Ssp (ch) Spi: 1
• I2c/sio (ch): 5
• Uart/sio (ch): 12
• Usb: -
• Can: -
• Ethernet: -
• External Bus Interface: Y
• Cs/wait Controller (ch): 4
• Dma Controller: 2
• 10-bit Da Converter: -
• 10-bit Ad Converter: 16
• 12-bit Ad Converter: -
• 16-bit Timer / Counter: 16
• Motor / Igbt Control: -
• Real Time Clock: 1
• Watchdog Timer: Y
• Osc Freq Detect: -
• Clock Gear: Y
• Low-power Hold Function: Y
• Remote Control Interface: Y
• Hardware Cec Controller: Y
• Comparators: -
• Low-voltage Detector: -
• Etm Hardware Trace: 4-bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Operating Temperature: -
• Number Of I /o: -
• Eeprom Size: -
• Oscillator Type: -
• Lead Free Status / Rohs Status: Details
• Other names: Q5704184A

7.5
Interrupts
7.5.2.3
the active level specified in the clock generator, and is notified to the CPU.
rupt request must be held at the active level until it is detected, otherwise the interrupt request will cease
to exist when the signal level changes from active to inactive.
el to the CPU until the interrupt request is cleared in the CG Interrupt Request Clear (CGICRCG) Regis-
ter. If a standby mode is exited without clearing the interrupt request, the same interrupt will be detected
again when normal operation is resumed. Be sure to clear each interrupt request in the ISR.
(7)
If an interrupt source is used for exiting a standby mode, an interrupt request is detected according to
An edge-triggered interrupt request, once detected, is held in the clock generator. A level-sensitive inter-
When the clock generator detects an interrupt request, it keeps sending the interrupt signal in "High" lev-
Detection by Clock Generator
not used for exiting a standby mode. However, an "High" pulse or "High"-level signal must be in-
put so that the CPU can detect it as an interrupt request. Also, be aware of the description of
"7.5.1.4 Precautions when using external interrupt pins".
rupt with the Interrupt Set-Enable Register. Each bit of the register is assigned to a single interrupt
source.
terrupt. Writing "1" to the corresponding bit of the Interrupt Set-Enable Register enables the inten-
ded interrupt.
are lost if pending interrupts are cleared. Thus, this operation is not necessary.
Note 1: m : corresponding bit
Note 2: PRIMASK register cannot be modified by the user access level.
Clock generator register
CGIMCGn<EMCGm>
CGICRCG<ICRCG>
CGIMCGn<INTmEN>
NVIC register
Interrupt Clear-Pending [m]
Interrupt Set-Pending [m]
Interrupt mask register
PRIMASK
Interrupt requests from external pins can be used without setting the clock generator if they are
Enable the interrupt by the CPU as shown below.
Clear the suspended interrupt in the Interrupt Clear-Pending Register. Enable the intended inter-
Writing "1" to the corresponding bit of the Interrupt Clear-Pending Register clears the suspended in-
To generate interrupts in the Interrupt Set-Pending Register setting, factors to trigger interrupts
At the end, PRIMASK register is zero cleared.
Note:n: register number / m: number assigned to interrupt source
Enabling interrupt by CPU
←
←
←
active level
Value corresponding to the interrupt to be used
"1" (interrupt enabled)
←
←
←
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"1"
"1"
"0"
TMPM362F10FG