TMPM362F10FG Toshiba, TMPM362F10FG Datasheet - Page 565

• Manufacturer Part Number: TMPM362F10FG
• Description: 32BIT MICROCONTROLLER
• Manufacturer: Toshiba
• Series: TX03r

Specifications of TMPM362F10FG

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 64MHz
• Connectivity: I²C, Microwire, SIO, SPI, SSP, UART/USART
• Peripherals: DMA, WDT
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 16x10b
• Package / Case: 144-LQFP
• Processor Series: TX03
• Core: ARM Cortex M3
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): 1024K
• Rom Type: Flash
• Ram (kbytes): 64K
• Number Of Pins: 144
• Package: LQFP(20x20)
• Vcc: 3V
• Cpu Mhz: 64
• Ssp (ch) Spi: 1
• I2c/sio (ch): 5
• Uart/sio (ch): 12
• Usb: -
• Can: -
• Ethernet: -
• External Bus Interface: Y
• Cs/wait Controller (ch): 4
• Dma Controller: 2
• 10-bit Da Converter: -
• 10-bit Ad Converter: 16
• 12-bit Ad Converter: -
• 16-bit Timer / Counter: 16
• Motor / Igbt Control: -
• Real Time Clock: 1
• Watchdog Timer: Y
• Osc Freq Detect: -
• Clock Gear: Y
• Low-power Hold Function: Y
• Remote Control Interface: Y
• Hardware Cec Controller: Y
• Comparators: -
• Low-voltage Detector: -
• Etm Hardware Trace: 4-bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Operating Temperature: -
• Number Of I /o: -
• Eeprom Size: -
• Oscillator Type: -
• Lead Free Status / Rohs Status: Details
• Other names: Q5704184A

(4)
width are required. If multiple factors are specified, reception is completed by the factor detected
first. Make sure to configure the reception completion settings.
To complete data reception, settings of detecting the maximum data bit cycle and excess low
Settings of Reception Completion
1. Completetion by the maximum data bit cycle
2. Completetion by detecting low width
the RMCxRCR2 <RMCDMAX[7:0]> bits.
in the <RMCDMAX[7:0]> bits, a maximum data bit cycle is detected. The detection com-
pletes reception and generates an interrupt.After interrupt inputs generated,
RMCxRSTAT< RMCDMAXIF > bit is set to "1".
ister of each <RMCEND1>, <RMCEND2>, <RMCEND3>.In this case when the number
of set reception bit agreed with the number of bit which received at the time of the out-
break of MAX on the number of receive data is set a RMCxEND 1 to 3 register of each
<RMCEND1>, <RMCEND2>, <RMCEND3>, it occurs by an MAX interrupt in data bit pe-
riod.
ue in <RMCEND1>, <RMCEND2>, <RMCEND3>, it wait for Leader Reception.
RMCxRCR2 <RMCLL[7:0]> bits.
fied, excess low width is detected. The detection completes reception and generates an inter-
rupt.
To complete reception by detecting a maximum data bit cycle, you need to configure
If the falling edge of the data bit cycle isn't monitored after time specified as threshold
To complete reception by setting the number of receive data is set a RMCxEND 1 to 3 reg-
As specified to RMCxEND3 to 1, it is able to set three kinds of the receive data bit.
When it can receive the Maximum Data bit , the number of bit is not match the setting val-
To complete reception by detecting the low width, you need to configure the
After the falling edge of the data bit is detected, if the signal stays low longer than speci-
After interrupt inputs generated, RMCxRSTAT<RMCLOIF> bit is set to "1."
If the falling edge of the data bit cycle is not monitored after time
specified as threshold,a maximum data bit cycle is detected.
The detection completes reception and generates an interrupt.
Threshold:<RMCDMAX[7:0]>
Page 541
The maximum data bit cycle interrupt
TMPM362F10FG