TMPM362F10FG Toshiba, TMPM362F10FG Datasheet - Page 640

• Manufacturer Part Number: TMPM362F10FG
• Description: 32BIT MICROCONTROLLER
• Manufacturer: Toshiba
• Series: TX03r

Specifications of TMPM362F10FG

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 64MHz
• Connectivity: I²C, Microwire, SIO, SPI, SSP, UART/USART
• Peripherals: DMA, WDT
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 16x10b
• Package / Case: 144-LQFP
• Processor Series: TX03
• Core: ARM Cortex M3
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): 1024K
• Rom Type: Flash
• Ram (kbytes): 64K
• Number Of Pins: 144
• Package: LQFP(20x20)
• Vcc: 3V
• Cpu Mhz: 64
• Ssp (ch) Spi: 1
• I2c/sio (ch): 5
• Uart/sio (ch): 12
• Usb: -
• Can: -
• Ethernet: -
• External Bus Interface: Y
• Cs/wait Controller (ch): 4
• Dma Controller: 2
• 10-bit Da Converter: -
• 10-bit Ad Converter: 16
• 12-bit Ad Converter: -
• 16-bit Timer / Counter: 16
• Motor / Igbt Control: -
• Real Time Clock: 1
• Watchdog Timer: Y
• Osc Freq Detect: -
• Clock Gear: Y
• Low-power Hold Function: Y
• Remote Control Interface: Y
• Hardware Cec Controller: Y
• Comparators: -
• Low-voltage Detector: -
• Etm Hardware Trace: 4-bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Operating Temperature: -
• Number Of I /o: -
• Eeprom Size: -
• Oscillator Type: -
• Lead Free Status / Rohs Status: Details
• Other names: Q5704184A

21.3
Detailed Description Register
7
6
5
4
3
2-0
Bit symbol
After reset
21.3.3.11
Bit
DIS1HZ
DIS16HZ
RSTTMR
RSTALM
−
−
Bit Symbol
and 16Hz interrupt is shown as below.
Note 1: A read-modify-write operation cannot be performed.
The setting of <DIS1HZ> and <DIS16MHZ>, RTCPAGER<ENAALM> used for alarm, 1Hz interrupt
DIS1HZ
RTCRESTR (Reset register (for PAGE0/1))
7
1
R/W
R/W
R/W
R/W
R
R/W
Type
DIS16HZ
6
1
1 Hz
0:Enable
1: Disable
16 Hz
0: Enable
1: Disable
[Write]
0: Don't care
1: Sec.counter reset
Resets the sec counter. The equest is sampled using low-speed clock.
[Read]
0: No reset request
1: RESET requested
If "1" is read, it indicates that RESET is being executed. If "0" is read, it indicates that the execution is
finished.
0:Don't care
1: Alarm reset
Initializes alarm registers (Minute column, hour column, day column and day of the week column) as
follows.
MInute:00, Hour:00, Day:01, Day of the week:Sunday
Read as 0.
Write "1".
RSTTMR
5
0
<DIS1HZ>
Page 616
RSTALM
1
0
1
4
0
<DIS16HZ>
Function
3
0
-
Others
1
1
0
2
1
-
RTCPAGER
<ENAALM>
1
0
0
1
1
-
TMPM362F10FG
Interrupt source
not generated.
Interrupt
16 Hz
signal
Alarm
1 Hz
0
1
-