TMPM362F10FG Toshiba, TMPM362F10FG Datasheet - Page 431

• Manufacturer Part Number: TMPM362F10FG
• Description: 32BIT MICROCONTROLLER
• Manufacturer: Toshiba
• Series: TX03r

Specifications of TMPM362F10FG

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 64MHz
• Connectivity: I²C, Microwire, SIO, SPI, SSP, UART/USART
• Peripherals: DMA, WDT
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 16x10b
• Package / Case: 144-LQFP
• Processor Series: TX03
• Core: ARM Cortex M3
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): 1024K
• Rom Type: Flash
• Ram (kbytes): 64K
• Number Of Pins: 144
• Package: LQFP(20x20)
• Vcc: 3V
• Cpu Mhz: 64
• Ssp (ch) Spi: 1
• I2c/sio (ch): 5
• Uart/sio (ch): 12
• Usb: -
• Can: -
• Ethernet: -
• External Bus Interface: Y
• Cs/wait Controller (ch): 4
• Dma Controller: 2
• 10-bit Da Converter: -
• 10-bit Ad Converter: 16
• 12-bit Ad Converter: -
• 16-bit Timer / Counter: 16
• Motor / Igbt Control: -
• Real Time Clock: 1
• Watchdog Timer: Y
• Osc Freq Detect: -
• Clock Gear: Y
• Low-power Hold Function: Y
• Remote Control Interface: Y
• Hardware Cec Controller: Y
• Comparators: -
• Low-voltage Detector: -
• Etm Hardware Trace: 4-bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Operating Temperature: -
• Number Of I /o: -
• Eeprom Size: -
• Oscillator Type: -
• Lead Free Status / Rohs Status: Details
• Other names: Q5704184A

12.14.2
TXD
12.14.2.1
12.14.2.2
Figure 12-11 shows the data flow of transmit operation and the route of read.
which are given as follows.
SCxTFC<TFIS> setting are established.
Table 12-14 Transmit Interrupt conditions in use of FIFO
If the transmit buffer is empty,
TX interrupt
SCxTFC<TFIS>
TX interrupts are generated at the time depends on the transfer mode and the buffer configurations,
In use of FIFO, transmit interrupt is generated on the condition that the following either operation and
Interrupt conditions are decided by the SCxTFC<TFIS> settings as described in Table 12-14.
Buffer Configuration
If the shift register is empty,
Note:If double buffer is enabled, a interrupt is also generated when the data is moved from the buf-
Double Buffer
Single Buffer
Single Buffer / Double Buffer
FIFO
Figure 12-11 Transmit Buffer / FIFO Configuration Diagram
・ Transmission completion of all bits of one frame.
・ Writing FIFO
"0"
"1"
fer to the shift register by writing to the buffer.
the data is moved.
the data is moved.
"The fill level of FIFO" is smaller than or equal to "the fill level of FIFO interruption generation."
TX FIFO First stage
Just before the stop bit is sent
When a data is moved from the transmit buffet to the transmit shift register.
Transmit shift register
"The fill level of FIFO" is equal to "the fill level of FIFO interruption generation."
Transmit buffer
UART modes
Second stage
Third stage
Fourth stage
Page 407
Interrupt condition
Immediately after the raising / falling edge of the last SCLK
(Rising or falling is determined according to SCxCR<SCLKS> setting.)
(1)Writing in the single buffer configuration :
(2)Writing in the double buffer configuration :
(3)Writing in use the FIFO :
An interrupt is generated after transmitting all bits.
An interrupt is generated when the data is moved to
the transmit shift register.
An interrupt is generated
When the data is moved to the transmit buffer
or when wrting to the FIFO.
I/O interface modes
TMPM362F10FG