TMPM362F10FG Toshiba, TMPM362F10FG Datasheet - Page 414
TMPM362F10FG
Manufacturer Part Number
TMPM362F10FG
Description
32BIT MICROCONTROLLER
Manufacturer
Toshiba
Series
TX03r
Datasheet
1.TMPM362F10FG.pdf
(744 pages)
Specifications of TMPM362F10FG
Core Processor
ARM® Cortex-M3™
Core Size
32-Bit
Speed
64MHz
Connectivity
I²C, Microwire, SIO, SPI, SSP, UART/USART
Peripherals
DMA, WDT
Program Memory Size
1MB (1M x 8)
Program Memory Type
FLASH
Ram Size
64K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 16x10b
Package / Case
144-LQFP
Processor Series
TX03
Core
ARM Cortex M3
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2
Product Summaries
Summary
Lead Free
Yes
Rohs Compatible Product(s)
Available
Rom (kbytes)
1024K
Rom Type
Flash
Ram (kbytes)
64K
Number Of Pins
144
Package
LQFP(20x20)
Vcc
3V
Cpu Mhz
64
Ssp (ch) Spi
1
I2c/sio (ch)
5
Uart/sio (ch)
12
Usb
-
Can
-
Ethernet
-
External Bus Interface
Y
Cs/wait Controller (ch)
4
Dma Controller
2
10-bit Da Converter
-
10-bit Ad Converter
16
12-bit Ad Converter
-
16-bit Timer / Counter
16
Motor / Igbt Control
-
Real Time Clock
1
Watchdog Timer
Y
Osc Freq Detect
-
Clock Gear
Y
Low-power Hold Function
Y
Remote Control Interface
Y
Hardware Cec Controller
Y
Comparators
-
Low-voltage Detector
-
Etm Hardware Trace
4-bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Operating Temperature
-
Number Of I /o
-
Eeprom Size
-
Oscillator Type
-
Lead Free Status / Rohs Status
Details
Other names
Q5704184A
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
TMPM362F10FG
Manufacturer:
Freescale
Quantity:
488
- Current page: 414 of 744
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12.7
Clock Control
Table 12-7 Clock selection in I/O interface Mode
(2)
I/O interface mode
SCxMOD0<SM>
ded by 16 in the receive counter or the transmit counter before use.
To get the highest baud rate, the baud rate generator must be set as below.
To use SCLK input, the following conditions must be satisfied.
Table 12-8 shows the clock selection in the UART mode. In the UART mode, selected clock is divi-
Mode
Note:When deciding clock settings, make sure that AC electrical character is satisfied.
Transfer clock in the UART mode
・ Clock / mode control block settings
・ SIO settings (if double buffer is used)
・ SIO settings (if double buffer is not used)
・ If double buffer is used
・ If double buffer is not used
10Mbps because 20MHz is divided by 2.
5Mbps because 10MHz is divided by 2.
-
-
-
-
-
-
-
1 division ratio can be selected if double buffer is used. In this case, baud rate is
2 division ratio is the highest if double buffer is not used. In this case, baud rate is
- SCLK cycle > 6/fsys
The highest buad rate is less than 40 ÷ 6 = 6.66 Mbps.
- SCLK cycle > 8/fsys
The highest baud rate is less than 40 ÷ 8 = 5.0 Mbps.
fc = 40MHz
fgear = 40MHz (CGSYSCR<GEAR[2:0]> = "000" : fc selected)
φT0=40Mhz (CGSYSCR<PRCK[2:0:]>="000" : 1 division ratio)
Clock (SCxBRCR<BRCK[1:0]> = "00" : φT1 selected) = 20MHz
Divided clock frequency (SCxBRCR<BRS[3:0]> = "0001":1 division ratio) = 20MHz
Clock (SCxBRCR<BRCK[1:0]> = "00":φT1 selected) = 20MHz
Divided clock frequency (SCxBRCR<BRS[3:0]> = "0010" : 2 division ratio) = 10MHz
Input / Output
SCxCR<IOC>
SCLK output
SCLK input
selection
Page 390
(Fixed to the rising edge)
Clock edge selection
SCxCR<SCLKS>
Rising edge
Falling edge
Set to "0"
Divided by 2 of the baud rate gen-
SCLK input falling edge
SCLK input rising edge
Clock of use
erator output
TMPM362F10FG
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