TMPM362F10FG Toshiba, TMPM362F10FG Datasheet - Page 427

• Manufacturer Part Number: TMPM362F10FG
• Description: 32BIT MICROCONTROLLER
• Manufacturer: Toshiba
• Series: TX03r

Specifications of TMPM362F10FG

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 64MHz
• Connectivity: I²C, Microwire, SIO, SPI, SSP, UART/USART
• Peripherals: DMA, WDT
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 16x10b
• Package / Case: 144-LQFP
• Processor Series: TX03
• Core: ARM Cortex M3
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): 1024K
• Rom Type: Flash
• Ram (kbytes): 64K
• Number Of Pins: 144
• Package: LQFP(20x20)
• Vcc: 3V
• Cpu Mhz: 64
• Ssp (ch) Spi: 1
• I2c/sio (ch): 5
• Uart/sio (ch): 12
• Usb: -
• Can: -
• Ethernet: -
• External Bus Interface: Y
• Cs/wait Controller (ch): 4
• Dma Controller: 2
• 10-bit Da Converter: -
• 10-bit Ad Converter: 16
• 12-bit Ad Converter: -
• 16-bit Timer / Counter: 16
• Motor / Igbt Control: -
• Real Time Clock: 1
• Watchdog Timer: Y
• Osc Freq Detect: -
• Clock Gear: Y
• Low-power Hold Function: Y
• Remote Control Interface: Y
• Hardware Cec Controller: Y
• Comparators: -
• Low-voltage Detector: -
• Etm Hardware Trace: 4-bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Operating Temperature: -
• Number Of I /o: -
• Eeprom Size: -
• Oscillator Type: -
• Lead Free Status / Rohs Status: Details
• Other names: Q5704184A

Transmit FIFO fourth stage
12.12.3.3
Transmit interrupt (INTTXx)
SCxMOD2<TBEMP>
Transmit shift register
SCxMOD1<TXE>
Transmit buffer
should lasts writing transmit data.
all data transmission is completed and underrun error will not occur.
age.
Second stage
Third stage
First stage
(1)
(2)
(3)
Once above settings are configured, if the transmission is not set as auto disabled, the transmission
If SCLK is set to generate clock in the I/O interface mode, the SCLK output automatically stops when
The timing of suspension and resume of SCLK output is different depending on the buffer and FIFO us-
I/O interface Mode/Transmission by SCLK Output
with the other side of communication can be enabled. The SCLK output resumes when the next da-
ta is written in the buffer.
the transmit buffer. The SCLK output resumes when the next data is written in the buffer.
ted, the SCLK output stops. The next data is written, SCLK output resumes.
SCLK stop and the transmission stops.
The SCLK output stops each time one frame of data is transferred. Handshaking for each data
The SCLK output stops upon completion of data transmission of the transmit shift register and
The transmission of all data stored in the transmit shift register, transmit buffer and FIFO is comple-
If SCxFCNF<RXTXCNT> is configured, SCxMOD0<TXE> bit is cleared at the same time as
Single Buffer
Double Buffer
FIFO
DATA 5
DATA 4
DATA 3
DATA 2
DATA 1
DATA 5
DATA 4
DATA 3
DATA 2
DATA 1
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DATA 5
DATA 4
DATA 3
DATA 2
DATA 5
DATA 4
DATA 3
DATA 5
DATA 4
TMPM362F10FG
DATA 5