TMPM362F10FG Toshiba, TMPM362F10FG Datasheet - Page 433

• Manufacturer Part Number: TMPM362F10FG
• Description: 32BIT MICROCONTROLLER
• Manufacturer: Toshiba
• Series: TX03r

Specifications of TMPM362F10FG

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 64MHz
• Connectivity: I²C, Microwire, SIO, SPI, SSP, UART/USART
• Peripherals: DMA, WDT
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 16x10b
• Package / Case: 144-LQFP
• Processor Series: TX03
• Core: ARM Cortex M3
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): 1024K
• Rom Type: Flash
• Ram (kbytes): 64K
• Number Of Pins: 144
• Package: LQFP(20x20)
• Vcc: 3V
• Cpu Mhz: 64
• Ssp (ch) Spi: 1
• I2c/sio (ch): 5
• Uart/sio (ch): 12
• Usb: -
• Can: -
• Ethernet: -
• External Bus Interface: Y
• Cs/wait Controller (ch): 4
• Dma Controller: 2
• 10-bit Da Converter: -
• 10-bit Ad Converter: 16
• 12-bit Ad Converter: -
• 16-bit Timer / Counter: 16
• Motor / Igbt Control: -
• Real Time Clock: 1
• Watchdog Timer: Y
• Osc Freq Detect: -
• Clock Gear: Y
• Low-power Hold Function: Y
• Remote Control Interface: Y
• Hardware Cec Controller: Y
• Comparators: -
• Low-voltage Detector: -
• Etm Hardware Trace: 4-bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Operating Temperature: -
• Number Of I /o: -
• Eeprom Size: -
• Oscillator Type: -
• Lead Free Status / Rohs Status: Details
• Other names: Q5704184A

12.16
12.16.1
12.16.1.1
mode to accept synchronous clock from an external source.
tion, refer to the previous sections describing receive/transmit FIFO functions.
Operation in Each Mode
Mode 0 consists of two modes, the SCLK output mode to output synchronous clock and the SCLK input
The following operational descriptions are for the case use of FIFO is disabled. For details of FIFO opera-
Mode 0 (I/O Interface Mode)
(1)
Transmitting Data
SCLK Output Mode
・ If the transmit double buffer is disabled (SCxMOD2<WBUF> = "0")
・ If the transmit double buffer is enabled (SCxMOD2<WBUF> = "1")
the CPU writes data to the transmit buffer. When all data is output, an interrupt (INTTXx)
is generated.
writes data to the transmit buffer while data transmission is halted or when data transmis-
sion from the transmit buffer (shift register) is completed. Simultaneously, the transmit buf-
fer empty flag SCxMOD2<TBEMP> is set to "1", and the INTTXx interrupt is generated.
mit buffer has no data to be moved to the transmit shift register, INTTXx interrupt is not gen-
erated and the SCLK output stops.
Data is output from the TXD pin and the clock is output from the SCLK pin each time
Data is moved from the transmit buffer to the transmit shift register when the CPU
When data is moved from the transmit buffer to the transmit shift register, if the trans-
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