TMPM362F10FG Toshiba, TMPM362F10FG Datasheet - Page 100

• Manufacturer Part Number: TMPM362F10FG
• Description: 32BIT MICROCONTROLLER
• Manufacturer: Toshiba
• Series: TX03r

Specifications of TMPM362F10FG

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 64MHz
• Connectivity: I²C, Microwire, SIO, SPI, SSP, UART/USART
• Peripherals: DMA, WDT
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 16x10b
• Package / Case: 144-LQFP
• Processor Series: TX03
• Core: ARM Cortex M3
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): 1024K
• Rom Type: Flash
• Ram (kbytes): 64K
• Number Of Pins: 144
• Package: LQFP(20x20)
• Vcc: 3V
• Cpu Mhz: 64
• Ssp (ch) Spi: 1
• I2c/sio (ch): 5
• Uart/sio (ch): 12
• Usb: -
• Can: -
• Ethernet: -
• External Bus Interface: Y
• Cs/wait Controller (ch): 4
• Dma Controller: 2
• 10-bit Da Converter: -
• 10-bit Ad Converter: 16
• 12-bit Ad Converter: -
• 16-bit Timer / Counter: 16
• Motor / Igbt Control: -
• Real Time Clock: 1
• Watchdog Timer: Y
• Osc Freq Detect: -
• Clock Gear: Y
• Low-power Hold Function: Y
• Remote Control Interface: Y
• Hardware Cec Controller: Y
• Comparators: -
• Low-voltage Detector: -
• Etm Hardware Trace: 4-bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Operating Temperature: -
• Number Of I /o: -
• Eeprom Size: -
• Oscillator Type: -
• Lead Free Status / Rohs Status: Details
• Other names: Q5704184A

7.5
Interrupts
7.5.2.2
expected interrupt on the way.
ly. Disable the interrupt by the CPU. Configure from the farthest route from the CPU. Then enable the in-
terrupt by the CPU.
ted interrupt. First, configure the precondition. Secondly, clear the data related to the interrupt in the
clock generator and then enable the interrupt.
(1)
(2)
When preparing for an interrupt, you need to pay attention to the order of configuration to avoid any un-
Initiating an interrupt or changing its configuration must be implemented in the following order basical-
To configure the clock generator, you must follow the order indicated here not to cause any unexpec-
The following sections are listed in the order of interrupt handling and describe how to configure them.
Preparation
MASK Register. All interrupts and exceptions other than non-maskable interrupts and hard faults
can be masked.
the NVIC register.
the number of bits actually used varies with each product.Priority level 0 is the highest priority lev-
el.If multiple sources have the same priority, the smallest-numbered interrupt source has the highest
priority.
Interrupt mask register
PRIMASK
1. Disabling interrupt by CPU
2. CPU registers setting
3. Preconfiguration (1) (Interrupt from external pin)
4. Preconfiguration (2) (Interrupt from peripheral function)
5. Preconfiguration (3) (Interrupt Set-Pending Register)
6. Configuring the clock generator
7. Enabling interrupt by CPU
Note 1: PRIMASK register cannot be modified by the user access level.
Note 2: If a fault causes when "1" is set to the PRIMASK register, it is treated as a hard fault.
To make the CPU for not accepting any interrupt, write "1" to the corresponding bit of the PRI-
Use "MSR" instruction to set this register.
You can assign a priority level by writing to <PRI_n> field in an Interrupt Priority Register of
Each interrupt source is provided with eight bits for assigning a priority level from 0 to 255, but
Disabling interrupt by CPU
CPU registers setting
←
"1"(Interrupt disabled)
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TMPM362F10FG