TMPM362F10FG Toshiba, TMPM362F10FG Datasheet - Page 521

• Manufacturer Part Number: TMPM362F10FG
• Description: 32BIT MICROCONTROLLER
• Manufacturer: Toshiba
• Series: TX03r

Specifications of TMPM362F10FG

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 64MHz
• Connectivity: I²C, Microwire, SIO, SPI, SSP, UART/USART
• Peripherals: DMA, WDT
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 16x10b
• Package / Case: 144-LQFP
• Processor Series: TX03
• Core: ARM Cortex M3
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): 1024K
• Rom Type: Flash
• Ram (kbytes): 64K
• Number Of Pins: 144
• Package: LQFP(20x20)
• Vcc: 3V
• Cpu Mhz: 64
• Ssp (ch) Spi: 1
• I2c/sio (ch): 5
• Uart/sio (ch): 12
• Usb: -
• Can: -
• Ethernet: -
• External Bus Interface: Y
• Cs/wait Controller (ch): 4
• Dma Controller: 2
• 10-bit Da Converter: -
• 10-bit Ad Converter: 16
• 12-bit Ad Converter: -
• 16-bit Timer / Counter: 16
• Motor / Igbt Control: -
• Real Time Clock: 1
• Watchdog Timer: Y
• Osc Freq Detect: -
• Clock Gear: Y
• Low-power Hold Function: Y
• Remote Control Interface: Y
• Hardware Cec Controller: Y
• Comparators: -
• Low-voltage Detector: -
• Etm Hardware Trace: 4-bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Operating Temperature: -
• Number Of I /o: -
• Eeprom Size: -
• Oscillator Type: -
• Lead Free Status / Rohs Status: Details
• Other names: Q5704184A

15.3.8
31-15
14-12
11
10-8
7
6-4
3
2-0
bit symbol
After reset
bit symbol
After reset
bit symbol
After reset
bit symbol
After reset
<CECSWAV3>:/
<CECSWAV2>:
<CECSWAV1>:/
<CECSWAV0>:
Bit
−
CECSWAV3[2:0]
−
CECSWAV2[2:0]
−
CECSWAV1[2:0]
−
CECSWAV0[2:0]
CECRCR2 (Receive Control Register 2)
Bit Symbol
31
23
15
0
0
0
7
0
-
-
-
-
Specifies the cycles to detect a start bit.
<CECSWAV3> is for the maximum cycles. The base time is 154/fs (approx.4.700 ms). Enables to specify it between the rang-
es 0 to +7/fs by the unit of 1/fs.
<CECSWAV2> is for the minimum cycles. The base time is 141/fs (approx.4.303 ms). Enables to specify it between the rang-
es 0 to -7/fs by the unit of 1/fs.
Specifies the rising timing of a start bit in its detection.
<CECSWAV1> is for the maximum time of the rising timing. The base time is 128/fs (approx.3.906 ms). Enables to specify
it between the ranges 0 to +7/fs by the unit of 1/fs.
<CECSWAV0> is for the minimum time of the rising timing. The base time is 115/fs (approx.3.510 ms). Enables to specify
it between the ranges 0 to -7/fs by the unit of 1/fs.
R
R/W
R
R/W
R
R/W
R
R/W
Type
30
22
14
0
0
0
6
0
-
-
Read as 0.
Max. cycle to detect start bit.
000: 154/fs (approx. 4.700 ms)
001: 154/fs + 1/fs
001: 154/fs + 2/fs
011: 154/fs + 3/fs
Read as 0.
Min. cycle to detect start bit.
000: 141/fs (approx. 4.303 ms)
001: 141/fs − 1/fs
001: 141/fs − 2/fs
011: 141/fs − 3/fs
Read as 0.
Max. time of start bit rising timing.
000: 128/fs (approx. 3.906 ms)
001: 128/fs + 1/fs
001: 128/fs + 2/fs
011: 128/fs + 3/fs
Read as 0.
Min. time of start bit rising timing.
000: 115/fs (approx. 3.510 ms)
001: 115/fs − 1/fs
001: 115/fs − 2/fs
011: 115/fs − 3/fs
CECSWAV3
CECSWAV1
29
21
13
0
0
0
5
0
-
-
Page 497
28
20
12
0
0
0
4
0
-
-
27
19
11
0
0
0
3
0
-
-
-
-
Function
100: 154/fs + 4/fs
101: 154/fs + 5/fs
110: 154/fs + 6/fs
111: 154/fs + 7/fs
100: 141/fs − 4/fs
101: 141/fs − 5/fs
110: 141/fs − 6/fs
111: 141/fs − 7/fs
100: 128/fs + 4/fs
101: 128/fs + 5/fs
110: 128/fs + 6/fs
111: 128/fs + 7/fs
100: 115/fs − 4/fs
101: 115/fs − 5/fs
110: 115/fs − 6/fs
111: 115/fs − 7/fs
26
18
10
0
0
0
2
0
-
-
CECSWAV2
CECSWAV0
25
17
0
0
9
0
1
0
-
-
TMPM362F10FG
24
16
0
0
8
0
0
0
-
-