TMPM362F10FG Toshiba, TMPM362F10FG Datasheet - Page 336
TMPM362F10FG
Manufacturer Part Number
TMPM362F10FG
Description
32BIT MICROCONTROLLER
Manufacturer
Toshiba
Series
TX03r
Datasheet
1.TMPM362F10FG.pdf
(744 pages)
Specifications of TMPM362F10FG
Core Processor
ARM® Cortex-M3™
Core Size
32-Bit
Speed
64MHz
Connectivity
I²C, Microwire, SIO, SPI, SSP, UART/USART
Peripherals
DMA, WDT
Program Memory Size
1MB (1M x 8)
Program Memory Type
FLASH
Ram Size
64K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 16x10b
Package / Case
144-LQFP
Processor Series
TX03
Core
ARM Cortex M3
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2
Product Summaries
Summary
Lead Free
Yes
Rohs Compatible Product(s)
Available
Rom (kbytes)
1024K
Rom Type
Flash
Ram (kbytes)
64K
Number Of Pins
144
Package
LQFP(20x20)
Vcc
3V
Cpu Mhz
64
Ssp (ch) Spi
1
I2c/sio (ch)
5
Uart/sio (ch)
12
Usb
-
Can
-
Ethernet
-
External Bus Interface
Y
Cs/wait Controller (ch)
4
Dma Controller
2
10-bit Da Converter
-
10-bit Ad Converter
16
12-bit Ad Converter
-
16-bit Timer / Counter
16
Motor / Igbt Control
-
Real Time Clock
1
Watchdog Timer
Y
Osc Freq Detect
-
Clock Gear
Y
Low-power Hold Function
Y
Remote Control Interface
Y
Hardware Cec Controller
Y
Comparators
-
Low-voltage Detector
-
Etm Hardware Trace
4-bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Operating Temperature
-
Number Of I /o
-
Eeprom Size
-
Oscillator Type
-
Lead Free Status / Rohs Status
Details
Other names
Q5704184A
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
TMPM362F10FG
Manufacturer:
Freescale
Quantity:
488
- Current page: 336 of 744
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10.3
Description of Registers
10.3.10
31-20
19-17
16-14
13-11
10-8
7-4
3-0
bit symbol
After reset
bit symbol
After reset
bit symbol
After reset
bit symbol
After reset
Bit
−
t_tr[2:0]
t_pc[2:0]
t_wp[2:0]
t_ceoe[2:0]
t_wc[3:0]
t_rc[3:0]
Bit Symbol
Note:Page access is not supported in multiplex bus mode. t
smc_sram_cycles0_3 (SMC SRAM Cycles Registers 0 <3>)
Undefined
Undefined
31
23
15
1
7
1
-
-
t_pc
W
R
R
R
R
R
R
Type
Undefined
Undefined
30
22
14
0
6
1
-
-
Write as "0".
Turn around cycle time
001 to 111 : SMCCLK × 1 clock to SMCCLK × 7 clock
Page cycle time (note)
001 to 111 : SMCCLK × 1 clock to SMCCLK × 7 clock
WE pulse cycle time
001 to 111 : SMCCLK × 1 clock to SMCCLK × 7 clock
Delay cycle time to OE assert
001 to 111 : SMCCLK × 1 clock to SMCCLK × 7 clock
Write cycle time
0011 to 1111 : SMCCLK × 3 clock to SMCCLK × 15 clock
Read cycle time
0010 to 1111 : SMCCLK × 2 clock to SMCCLK × 15 clock
t_wc
Undefined
Undefined
29
21
13
1
5
0
-
-
Page 312
Undefined
Undefined
t_wp
28
20
12
1
4
0
-
-
Undefined
PC
27
19
11
Function
0
0
3
1
-
is effective only separate bus mode.
Undefined
t_tr
26
18
10
0
0
2
1
-
t_rc
Undefined
t_ceoe
25
17
1
9
1
1
0
-
TMPM362F10FG
Undefined
t_pc
24
16
0
8
1
0
0
-
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