TMPM362F10FG Toshiba, TMPM362F10FG Datasheet - Page 675

• Manufacturer Part Number: TMPM362F10FG
• Description: 32BIT MICROCONTROLLER
• Manufacturer: Toshiba
• Series: TX03r

Specifications of TMPM362F10FG

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 64MHz
• Connectivity: I²C, Microwire, SIO, SPI, SSP, UART/USART
• Peripherals: DMA, WDT
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 16x10b
• Package / Case: 144-LQFP
• Processor Series: TX03
• Core: ARM Cortex M3
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): 1024K
• Rom Type: Flash
• Ram (kbytes): 64K
• Number Of Pins: 144
• Package: LQFP(20x20)
• Vcc: 3V
• Cpu Mhz: 64
• Ssp (ch) Spi: 1
• I2c/sio (ch): 5
• Uart/sio (ch): 12
• Usb: -
• Can: -
• Ethernet: -
• External Bus Interface: Y
• Cs/wait Controller (ch): 4
• Dma Controller: 2
• 10-bit Da Converter: -
• 10-bit Ad Converter: 16
• 12-bit Ad Converter: -
• 16-bit Timer / Counter: 16
• Motor / Igbt Control: -
• Real Time Clock: 1
• Watchdog Timer: Y
• Osc Freq Detect: -
• Clock Gear: Y
• Low-power Hold Function: Y
• Remote Control Interface: Y
• Hardware Cec Controller: Y
• Comparators: -
• Low-voltage Detector: -
• Etm Hardware Trace: 4-bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Operating Temperature: -
• Number Of I /o: -
• Eeprom Size: -
• Oscillator Type: -
• Lead Free Status / Rohs Status: Details
• Other names: Q5704184A

3. The 3rd byte transmitted from the controller to the target board is a command. The code for
4. The 4th byte, transmitted from the target board to the controller, is an acknowledge response
5. The 5th to 16th bytes transmitted from the controller to the target board, are a 12-byte pass-
6. The 17th byte is a checksum value for the password sequence (5th to 16th bytes). To calculate
7. The 18th byte, transmitted from the target board to the controller, is an acknowledge response
the RAM Transfer command is 0x10.
to the 3rd byte. Before sending back the acknowledge response, the boot program checks for a
receive error. If there is a receive error, the boot program transmits 0xX8 (bit 3) and returns to
the state in which it waits for a command (the third byte) again. In this case, the upper four
bits of the acknowledge response are undefined - they hold the same values as the upper four
bits of the previously issued command. When the SIO0 is configured for I/O Interface mode,
the boot program does not check for a receive error.
echoes it back to the controller. When the RAM Transfer command is received, the boot pro-
gram echoes back a value of 0x10 and then branches to the RAM Transfer routine. Once this
branch is taken, password verification is done. Password verification is detailed in the later Sec-
tion "Password". If the 3rd byte is not a valid command, the boot program sends back 0xX1
(bit 0) to the controller and returns to the state in which it waits for a command (the third
byte) again. In this case, the upper four bits of the acknowledge response are undefined - they
hold the same values as the upper four bits of the previously issued command.
word. Each byte is compared to the contents of following addresses in the flash memory. The ver-
ification is started with the 5th byte. If the password verification fails, the RAM Transfer rou-
tine sets the password error flag.
the checksum value for the 12-byte password, add the 12 bytes together, ignore the carries and
caluculate the 8-bit two's complement by using lower 8 bits then transmit this checksum value
from the controller. The checksum calculation is described in details in the later Section "Check-
sum Calculation".
to the 5th to 17th bytes. First, the RAM Transfer routine checks for a receive error in the 5th
to 17th byte. If there is a receive error, the boot program sends back 0x18 (bit 3) and returns
to the state in which it waits for a command (i.e., the 3rd byte) again. In this case, the upper
four bits of the acknowledge response are the same as those of the previously issued com-
mand (i.e., 1). When the SIO4 is configured for I/O Interface mode, the RAM Transfer rou-
tine does not check for a receive error.
tegrity. Adding the series of the 5th to 16th bytes must result in 0x00 (with the carry drop-
ped). In case of a checksum error, the RAM Transfer routine sends back 0x11 to the control-
ler and returns to the state in which it waits for a command (i.e., the 3rd byte) again.
boot program transmits an acknowledge response (bit 0, 0x11) as a password error and waits
for next operation command (3rd byte).
mal acknowledge response (0x10) to the controller.
・ Irrespective of the result of the password comparison, all the 12 bytes of a password in
・ Not the entire password bytes transmitted from the controller matched those contained in
If the 3rd byte is equal to any of the command codes listed in Table 22-4, the boot program
Next, the RAM Transfer routine performs the checksum operation to ensure 17th byte data in-
Finally, the password verification result is checked. If the following case is generated, the
When all the above verification has been successful, the RAM Transfer routine returns a nor-
the flash memory are the same value other than 0xFF.
the flash memory.
TMPM362F10FG
Product name
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TMPM362F10FG