TMPM362F10FG Toshiba, TMPM362F10FG Datasheet - Page 480
TMPM362F10FG
Manufacturer Part Number
TMPM362F10FG
Description
32BIT MICROCONTROLLER
Manufacturer
Toshiba
Series
TX03r
Datasheet
1.TMPM362F10FG.pdf
(744 pages)
Specifications of TMPM362F10FG
Core Processor
ARM® Cortex-M3™
Core Size
32-Bit
Speed
64MHz
Connectivity
I²C, Microwire, SIO, SPI, SSP, UART/USART
Peripherals
DMA, WDT
Program Memory Size
1MB (1M x 8)
Program Memory Type
FLASH
Ram Size
64K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 16x10b
Package / Case
144-LQFP
Processor Series
TX03
Core
ARM Cortex M3
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2
Product Summaries
Summary
Lead Free
Yes
Rohs Compatible Product(s)
Available
Rom (kbytes)
1024K
Rom Type
Flash
Ram (kbytes)
64K
Number Of Pins
144
Package
LQFP(20x20)
Vcc
3V
Cpu Mhz
64
Ssp (ch) Spi
1
I2c/sio (ch)
5
Uart/sio (ch)
12
Usb
-
Can
-
Ethernet
-
External Bus Interface
Y
Cs/wait Controller (ch)
4
Dma Controller
2
10-bit Da Converter
-
10-bit Ad Converter
16
12-bit Ad Converter
-
16-bit Timer / Counter
16
Motor / Igbt Control
-
Real Time Clock
1
Watchdog Timer
Y
Osc Freq Detect
-
Clock Gear
Y
Low-power Hold Function
Y
Remote Control Interface
Y
Hardware Cec Controller
Y
Comparators
-
Low-voltage Detector
-
Etm Hardware Trace
4-bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Operating Temperature
-
Number Of I /o
-
Eeprom Size
-
Oscillator Type
-
Lead Free Status / Rohs Status
Details
Other names
Q5704184A
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
TMPM362F10FG
Manufacturer:
Freescale
Quantity:
488
- Current page: 480 of 744
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14.4
Control Registers in the I2C Bus Mode
14.4.5
14.4.6
31-8
7
6
5-1
0
31-8
7-0
bit symbol
After reset
bit symbol
After reset
bit symbol
After reset
bit symbol
After reset
bit symbol
After reset
bit symbol
After reset
bit symbol
After reset
bit symbol
After reset
Bit
Bit
-
-
I2SBI
-
-
-
DB[7:0]
Note 1: The transmission data must be written in to the register from the MSB (bit 7). The received data is stor-
Note 2: Since SBIxBDR has independent buffers for writing and reading, a written data cannot be read. Thus, read-
Bit Symbol
Bit Symbol
SBIxBR0(Serial bus interface baud rate register 0)
SBIxDBR (Serial bus interface data buffer register)
31
23
15
31
23
15
0
0
0
7
1
0
0
0
7
0
-
-
-
-
-
-
-
ed in the LSB.
modify-write instructions, such as bit manipulation, cannot be used.
R
R
R/W
R
R/W
R
R (Receive)/
W (Transmit)
Type
Type
I2SBI
30
22
14
30
22
14
0
0
0
6
0
0
0
0
6
0
-
-
-
Read as 0.
Read as 1.
Operation at the IDLE mode
0: Stop
1: Operate
Read as 1.
Be sure to write "0".
-
-
-
Read as 0.
Receive data /
Transmit data
29
21
13
29
21
13
0
0
0
5
1
0
0
0
5
0
-
-
-
-
-
-
-
Page 456
28
20
12
28
20
12
0
0
0
4
1
0
0
0
4
0
-
-
-
-
-
-
-
DB
27
19
11
27
19
11
Function
0
0
0
3
1
0
0
0
3
0
-
-
-
-
-
-
-
Function
26
18
10
26
18
10
0
0
0
2
1
0
0
0
2
0
-
-
-
-
-
-
-
25
17
25
17
0
0
9
0
1
1
0
0
9
0
1
0
-
-
-
-
-
-
-
TMPM362F10FG
24
16
24
16
0
0
8
0
0
0
0
0
8
0
0
0
-
-
-
-
-
-
-
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