TMPM362F10FG Toshiba, TMPM362F10FG Datasheet - Page 690

• Manufacturer Part Number: TMPM362F10FG
• Description: 32BIT MICROCONTROLLER
• Manufacturer: Toshiba
• Series: TX03r

Specifications of TMPM362F10FG

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 64MHz
• Connectivity: I²C, Microwire, SIO, SPI, SSP, UART/USART
• Peripherals: DMA, WDT
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 16x10b
• Package / Case: 144-LQFP
• Processor Series: TX03
• Core: ARM Cortex M3
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): 1024K
• Rom Type: Flash
• Ram (kbytes): 64K
• Number Of Pins: 144
• Package: LQFP(20x20)
• Vcc: 3V
• Cpu Mhz: 64
• Ssp (ch) Spi: 1
• I2c/sio (ch): 5
• Uart/sio (ch): 12
• Usb: -
• Can: -
• Ethernet: -
• External Bus Interface: Y
• Cs/wait Controller (ch): 4
• Dma Controller: 2
• 10-bit Da Converter: -
• 10-bit Ad Converter: 16
• 12-bit Ad Converter: -
• 16-bit Timer / Counter: 16
• Motor / Igbt Control: -
• Real Time Clock: 1
• Watchdog Timer: Y
• Osc Freq Detect: -
• Clock Gear: Y
• Low-power Hold Function: Y
• Remote Control Interface: Y
• Hardware Cec Controller: Y
• Comparators: -
• Low-voltage Detector: -
• Etm Hardware Trace: 4-bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Operating Temperature: -
• Number Of I /o: -
• Eeprom Size: -
• Oscillator Type: -
• Lead Free Status / Rohs Status: Details
• Other names: Q5704184A

22.3
On-board Programming of Flash Memory (Rewrite/Erase)
22.3.1.2
read mode. In the automatic operation mode, flash memory data cannot be read and any commands stor-
ed in the flash memory cannot be executed. In the automatic operation mode, any interrupt or exception gen-
eration cannot set the device to the read mode except when a hardware reset is generated. During automat-
ic operation, be sure not to cause any exception other than reset and debug exceptions while a debug port
is connected. Any exception generation cannot set the device to the read mode except when a hardware re-
set is generated.
(1)
(2)
This flash memory device has the following two operation modes:
Transition to the automatic mode is made by executing a command sequence while it is in the memory
Basic Operation
be set to the read mode immediately after power is applied, when CPU reset is removed, or when
an automatic operation is normally terminated. In order to return to the read mode from other
modes or after an automatic operation has been abnormally terminated, either the Read/reset com-
mand (a software command to be described later) or a hardware reset is used. The device must also
be in the read mode when any command written on the flash memory is to be executed.
mand sequence to the flash memory. The flash memory executes automatic operation commands ac-
cording to the address and data combinations applied (refer to Command Sequence).
mand sequence has been entered, the Read/reset command is to be executed. Then, the flash memo-
ry will terminate the command execution and return to the read.
32-bit (word) data transmission command to the flash memory is called "bus write cycle". The bus
write cycles have a specific sequential order and the flash memory will perform an automatic opera-
tion when the sequence of the bus write cycle data and address of command write is operated in accord-
ance with a predefined specific order. If any bus write cycle does not follow a predefined command
write sequence, the flash memory will terminate the command execution and return to the read mode.
・ The mode to read memory data (Read mode)
・ The mode to automatically erase or rewrite memory data (Automatic operation)
Note 1: Command sequences are executed from outside the flash memory area.
Note 2: Each bus write cycle must be sequentially executed by 32-bit data transmit command.
When data is to be read, the flash memory must be set to the read mode. The flash memory will
This flash memory uses the command control method. Commands are executed by executing a com-
If it is desired to cancel a command write operation already in progress or when any incorrect com-
While commands are generally comprised of several bus cycles and the operation applying to the
Read
Command write
・ Read / reset command and Read command (software reset)
・ With the Read/reset command, the device is returned to the read mode after completing
ically returning to the read mode. In this case, the Read/reset command can be used to re-
turn the flash memory to the read mode. Also, when a command that has not been complete-
ly written has to be canceled, the Read/reset command must be used. The Read command
is used to return to the read mode after executing 32-bit data transfer command to write
the data "0x0000_00F0" to an arbitrary address of the flash memory.
the third bus write cycle.
While a command sequence is being executed, access to the flash memory is prohibi-
ted. Also, do not generate any interrupt (except debug exceptions when a debug port is
connected). If such an operation is made, it may result in an unexpected read access to
the flash memory, and the command sequencer may not be able to correctly recognize
When ID-Read command is used, the reading operation is terminated instead of automat-
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