TMPM362F10FG Toshiba, TMPM362F10FG Datasheet - Page 127
TMPM362F10FG
Manufacturer Part Number
TMPM362F10FG
Description
32BIT MICROCONTROLLER
Manufacturer
Toshiba
Series
TX03r
Datasheet
1.TMPM362F10FG.pdf
(744 pages)
Specifications of TMPM362F10FG
Core Processor
ARM® Cortex-M3™
Core Size
32-Bit
Speed
64MHz
Connectivity
I²C, Microwire, SIO, SPI, SSP, UART/USART
Peripherals
DMA, WDT
Program Memory Size
1MB (1M x 8)
Program Memory Type
FLASH
Ram Size
64K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 16x10b
Package / Case
144-LQFP
Processor Series
TX03
Core
ARM Cortex M3
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2
Product Summaries
Summary
Lead Free
Yes
Rohs Compatible Product(s)
Available
Rom (kbytes)
1024K
Rom Type
Flash
Ram (kbytes)
64K
Number Of Pins
144
Package
LQFP(20x20)
Vcc
3V
Cpu Mhz
64
Ssp (ch) Spi
1
I2c/sio (ch)
5
Uart/sio (ch)
12
Usb
-
Can
-
Ethernet
-
External Bus Interface
Y
Cs/wait Controller (ch)
4
Dma Controller
2
10-bit Da Converter
-
10-bit Ad Converter
16
12-bit Ad Converter
-
16-bit Timer / Counter
16
Motor / Igbt Control
-
Real Time Clock
1
Watchdog Timer
Y
Osc Freq Detect
-
Clock Gear
Y
Low-power Hold Function
Y
Remote Control Interface
Y
Hardware Cec Controller
Y
Comparators
-
Low-voltage Detector
-
Etm Hardware Trace
4-bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Operating Temperature
-
Number Of I /o
-
Eeprom Size
-
Oscillator Type
-
Lead Free Status / Rohs Status
Details
Other names
Q5704184A
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
TMPM362F10FG
Manufacturer:
Freescale
Quantity:
488
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31-16
15
14-11
10-8
7-3
2
1
0
bit symbol
After reset
bit symbol
After reset
bit symbol
After reset
bit symbol
After reset
Bit
7.6.2.23
VECTKEY
(Written) /
VECTKEYSTAT
(Read)
ENDIANESS
−
PRIGROUP
−
SYSRESET
REQ
VECTCLR
ACTIVE
VECTRESET
Bit Symbol
ENDIANESS
Note 1: Little-endian is the default memory format for this product.
Note 2: When SYSRESETREQ is output, warm reset is performed on this product. <SYSRESETREQ>
Application Interrupt and Reset Control Register
31
23
15
0
0
0
7
0
-
is cleared by warm reset.
R/W
R/W
R
R/W
R
R/W
R/W
R/W
Type
30
22
14
0
0
0
6
0
Register key
[Write] Writing to this register requires 0x5FA in the <VECTKEY> field.
[Read] Read as 0xFA05.
Endianness bit: (Note1)
1: Big endian
0: Little endianl
Read as 0,
Interrupt priority grouping
000: seven bits of pre-emption priority, one bit of subpriority
001: six bits of pre-emption priority, two bits of subpriority
010: five bits of pre-emption priority, three bits of subpriority
011: four bits of pre-emption priority, four bits of subpriority
100: three bits of pre-emption priority, five bits of subpriority
101: two bits of pre-emption priority, six bits of subpriority
110: one bit of pre-emption priority, seven bits of subpriority
111: no pre-emption priority, eight bits of subpriority
The bit configuration to split the interrupt priority register <PRI_n> into pre-emption priority and sub priority.
Read as 0,
System Reset Request
1=CPU outputs a SYSRESETREQ signal. (note2)
Clear active vector bit
1: clear all state information for active NMI, fault, and interrupts.
0: do not clear.
This bit self-clears.
It it the responsibility of the application to reinitialize the stack.
System Reset bit
1: reset system.
0: do not reset system.
Resets the system, with the exception of debug components (FPB, DWT and ITM) by setting "1" and this
bit is also zero cleared.
-
-
29
21
13
0
0
0
5
0
-
-
Page 103
VECTKEY/VECTKEYSTAT
VECTKEY/VECTKEYSTAT
28
20
12
0
0
0
4
0
-
-
27
19
11
Function
0
0
0
3
0
-
-
SYSRESET
REQ
26
18
10
0
0
0
2
0
PRIGROUP
VECTCLR
ACTIVE
25
17
0
0
9
0
1
0
TMPM362F10FG
VECTRESET
24
16
0
0
8
0
0
0
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