TMPM362F10FG Toshiba, TMPM362F10FG Datasheet - Page 545
TMPM362F10FG
Manufacturer Part Number
TMPM362F10FG
Description
32BIT MICROCONTROLLER
Manufacturer
Toshiba
Series
TX03r
Datasheet
1.TMPM362F10FG.pdf
(744 pages)
Specifications of TMPM362F10FG
Core Processor
ARM® Cortex-M3™
Core Size
32-Bit
Speed
64MHz
Connectivity
I²C, Microwire, SIO, SPI, SSP, UART/USART
Peripherals
DMA, WDT
Program Memory Size
1MB (1M x 8)
Program Memory Type
FLASH
Ram Size
64K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 16x10b
Package / Case
144-LQFP
Processor Series
TX03
Core
ARM Cortex M3
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2
Product Summaries
Summary
Lead Free
Yes
Rohs Compatible Product(s)
Available
Rom (kbytes)
1024K
Rom Type
Flash
Ram (kbytes)
64K
Number Of Pins
144
Package
LQFP(20x20)
Vcc
3V
Cpu Mhz
64
Ssp (ch) Spi
1
I2c/sio (ch)
5
Uart/sio (ch)
12
Usb
-
Can
-
Ethernet
-
External Bus Interface
Y
Cs/wait Controller (ch)
4
Dma Controller
2
10-bit Da Converter
-
10-bit Ad Converter
16
12-bit Ad Converter
-
16-bit Timer / Counter
16
Motor / Igbt Control
-
Real Time Clock
1
Watchdog Timer
Y
Osc Freq Detect
-
Clock Gear
Y
Low-power Hold Function
Y
Remote Control Interface
Y
Hardware Cec Controller
Y
Comparators
-
Low-voltage Detector
-
Etm Hardware Trace
4-bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Operating Temperature
-
Number Of I /o
-
Eeprom Size
-
Oscillator Type
-
Lead Free Status / Rohs Status
Details
Other names
Q5704184A
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
TMPM362F10FG
Manufacturer:
Freescale
Quantity:
488
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15.4.3.5
15.4.3.6
pletion interrupt.
mission.
of starting the transmission.
(2)
(3)
(4)
To stop transmission, send data including the EOM bit that indicates "1". This generates a transmit com-
Please note that proper operation is not ensured if the start bit of transmission is set to "0" during trans-
Transmission is stopped by error detection. To retry the transmission, configure the condition and data
Stopping Transmission
Retransmission
fied in the CECTCR <CECBRD> bit.
mission of a byte of data, the transmit buffer underrun has priority.
An ACK error interrupt occurs when an ACK response does not conform to the configuration speci-
When the ACK error interrupt occurs, the CECTSTAT <CECTIACK> bit is set.
The ACK error is detected in the following cases.
A transmit buffer underrun error is caused by the following sequence.
1. Data in the transmit buffer is transmit to the shift register.
2. An interrupt occurs.
3. A byte of data is transmitted.
4. No data is set to the transmit buffer before starting transmission of a byte of subsequent data.
When an underrun error occurs, the CECTSTAT <CECTIUR> bit is set.
If interrupt factors of the ACK error and transmit buffer underrun are detected at the end of trans-
The transmit buffer underrun interrupt occurs first and then the ACK error interrupt occurs.
ACK error
Transmit Buffer Underrun
Order of ACK Error and Transmit Buffer Overrun
Broadcast transmission?: Yes
Broadcast transmission?: No
<CECBRD> = 0
<CECBRD> = 1
Configuration
Page 521
ACK response is logical "1"
ACK response is logical "0"
Determined as an ACK error when
TMPM362F10FG
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