TMPM362F10FG Toshiba, TMPM362F10FG Datasheet - Page 398

• Manufacturer Part Number: TMPM362F10FG
• Description: 32BIT MICROCONTROLLER
• Manufacturer: Toshiba
• Series: TX03r

Specifications of TMPM362F10FG

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 64MHz
• Connectivity: I²C, Microwire, SIO, SPI, SSP, UART/USART
• Peripherals: DMA, WDT
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 16x10b
• Package / Case: 144-LQFP
• Processor Series: TX03
• Core: ARM Cortex M3
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): 1024K
• Rom Type: Flash
• Ram (kbytes): 64K
• Number Of Pins: 144
• Package: LQFP(20x20)
• Vcc: 3V
• Cpu Mhz: 64
• Ssp (ch) Spi: 1
• I2c/sio (ch): 5
• Uart/sio (ch): 12
• Usb: -
• Can: -
• Ethernet: -
• External Bus Interface: Y
• Cs/wait Controller (ch): 4
• Dma Controller: 2
• 10-bit Da Converter: -
• 10-bit Ad Converter: 16
• 12-bit Ad Converter: -
• 16-bit Timer / Counter: 16
• Motor / Igbt Control: -
• Real Time Clock: 1
• Watchdog Timer: Y
• Osc Freq Detect: -
• Clock Gear: Y
• Low-power Hold Function: Y
• Remote Control Interface: Y
• Hardware Cec Controller: Y
• Comparators: -
• Low-voltage Detector: -
• Etm Hardware Trace: 4-bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Operating Temperature: -
• Number Of I /o: -
• Eeprom Size: -
• Oscillator Type: -
• Lead Free Status / Rohs Status: Details
• Other names: Q5704184A

12.4
Registers Description
12.4.9
31-8
7-5
4
3
2
1
0
After reset
After reset
After reset
After reset
bit symbol
bit symbol
bit symbol
bit symbol
Note 1: Regarding TX FIFO, the maximum number of bytes being configured is always available. The available num-
Note 2: The FIFO can not use in 9bit UART mode.
Bit
SCxFCNF (FIFO Configuration Register)
-
-
RFST
TFIE
RFIE
RXTXCNT
CNFG
ber of bytes is the bytes already written to the TX FIFO.
Bit Symbol
31
23
15
0
0
0
7
0
-
-
-
-
R
R/W
R/W
R/W
R/W
R/W
R/W
Type
30
22
14
0
0
0
6
0
-
-
-
-
Read as "0".
Be sure to write "000".
Bytes used in RX FIFO
0: Maximum
1: Same as FILL level of RX FIFO
When RX FIFO is enabled, the number of RX FIFO bytes to be used is selected (Note1)
0: The maximum number of bytes of the FIFO configured (see also <CNFG>).
1: Same as the fill level for receive interrupt generation specified by SCxRFC <RIL[1:0]>
TX interrupt for TX FIFO
0:Disabled
1:Enabled
When TX FIFO is enabled, transmit interrupts are enabled or disabled by this parameter.
RX interrupt for RX FIFO
0:Disabled
1:Enabled
When RX FIFO is enabled, receive interrupts are enabled or disabled by this parameter.
Automatic disable of RXE / TXE
0: None
1: Auto disabled
Controls automatic disabling of transmission and reception.
Setting "1" enables to operate as follows
Enables FIFO
0: Disabled
1: Enabled
Enabled bit for FIFO. (note2)
If <CNFG> is set to "1", the SCxMOD1 <FDPX[1:0]> setting automatically configures FIFO as follows:
Half duplex RX
Half duplex RX
Half duplex TX
Half duplex TX
Full duplex
Full duplex
29
21
13
0
0
0
5
0
-
-
-
-
When receive shift register, the receive buffer and the RX FIFO are filled,
SCxMOD0<RXE> is automatically set to "0" to inhibit further reception.
When the TX FIFO, the transmit buffer and the transmit shift register is empty,
SCxMOD1<TXE> is automatically set to "0" to inhibit further transmission.
When either of the above two conditions is satisfied, TXE/RXE are automatical-
ly set to "0" to inhibit further transmission and reception.
RX FIFO 4 bytes
TX FIFO 4 bytes
RX FIFO 2 bytes + TX FIFO 2 bytes
Page 374
RFST
28
20
12
0
0
0
4
0
-
-
-
TFIE
27
19
11
Function
0
0
0
3
0
-
-
-
RFIE
26
18
10
0
0
0
2
0
-
-
-
RXTXCNT
TMPM362F10FG
25
17
0
0
9
0
1
0
-
-
-
CNFG
24
16
0
0
8
0
0
0
-
-
-