TMPM362F10FG Toshiba, TMPM362F10FG Datasheet - Page 19
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TMPM362F10FG
Manufacturer Part Number
TMPM362F10FG
Description
32BIT MICROCONTROLLER
Manufacturer
Toshiba
Series
TX03r
Datasheet
1.TMPM362F10FG.pdf
(744 pages)
Specifications of TMPM362F10FG
Core Processor
ARM® Cortex-M3™
Core Size
32-Bit
Speed
64MHz
Connectivity
I²C, Microwire, SIO, SPI, SSP, UART/USART
Peripherals
DMA, WDT
Program Memory Size
1MB (1M x 8)
Program Memory Type
FLASH
Ram Size
64K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 16x10b
Package / Case
144-LQFP
Processor Series
TX03
Core
ARM Cortex M3
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2
Product Summaries
Summary
Lead Free
Yes
Rohs Compatible Product(s)
Available
Rom (kbytes)
1024K
Rom Type
Flash
Ram (kbytes)
64K
Number Of Pins
144
Package
LQFP(20x20)
Vcc
3V
Cpu Mhz
64
Ssp (ch) Spi
1
I2c/sio (ch)
5
Uart/sio (ch)
12
Usb
-
Can
-
Ethernet
-
External Bus Interface
Y
Cs/wait Controller (ch)
4
Dma Controller
2
10-bit Da Converter
-
10-bit Ad Converter
16
12-bit Ad Converter
-
16-bit Timer / Counter
16
Motor / Igbt Control
-
Real Time Clock
1
Watchdog Timer
Y
Osc Freq Detect
-
Clock Gear
Y
Low-power Hold Function
Y
Remote Control Interface
Y
Hardware Cec Controller
Y
Comparators
-
Low-voltage Detector
-
Etm Hardware Trace
4-bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Operating Temperature
-
Number Of I /o
-
Eeprom Size
-
Oscillator Type
-
Lead Free Status / Rohs Status
Details
Other names
Q5704184A
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
TMPM362F10FG
Manufacturer:
Freescale
Quantity:
488
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15. Consumer Electronics Control (CEC)
14.7 Control register of SIO mode..............................................................................................474
14.8 Control in SIO mode...........................................................................................................480
15.1 Outline.................................................................................................................................487
15.2 Block Diagram.....................................................................................................................488
15.3 Registers..............................................................................................................................489
15.4 Operations............................................................................................................................508
14.6.3
14.6.4
14.6.5
14.7.1
14.7.2
14.7.3
14.7.4
14.7.5
14.7.6
14.8.1
14.8.2
15.1.1
15.1.2
15.1.3
15.3.1
15.3.2
15.3.3
15.3.4
15.3.5
15.3.6
15.3.7
15.3.8
15.3.9
15.3.10
15.3.11
15.3.12
15.3.13
15.3.14
15.3.15
15.4.1
15.4.2
15.4.3
15.4.4
14.6.2.1
14.6.2.2
14.6.3.1
14.6.3.2
14.8.1.1
14.8.1.2
14.8.2.1
14.8.2.2
14.8.2.3
14.8.2.4
15.4.2.1
15.4.2.2
15.4.2.3
15.4.2.4
15.4.2.5
15.4.2.6
15.4.3.1
15.4.3.2
15.4.3.3
15.4.3.4
15.4.3.5
15.4.3.6
Transferring a Data Word.............................................................................................................................................467
Generating the Stop Condition......................................................................................................................................472
Restart Procedure...........................................................................................................................................................472
SBIxCR0(control register 0).........................................................................................................................................474
SBIxCR1(Control register 1)........................................................................................................................................475
SBIxDBR (Data buffer register)...................................................................................................................................476
SBIxCR2(Control register 2)........................................................................................................................................477
SBIxSR (Status Register)..............................................................................................................................................478
SBIxBR0 (Baud rate register 0)....................................................................................................................................479
Serial Clock...................................................................................................................................................................480
Transfer Modes..............................................................................................................................................................482
Reception.......................................................................................................................................................................487
Transmission..................................................................................................................................................................487
Precautions.....................................................................................................................................................................487
Register List...................................................................................................................................................................489
CECEN (CEC Enable Register)....................................................................................................................................490
CECADD (Logical Address Register ).........................................................................................................................491
CECRESET (Software Reset Register)........................................................................................................................492
CECREN (Receive Enable Register)............................................................................................................................493
CECRBUF (Receive Buffer Register)..........................................................................................................................494
CECRCR1 (Receive Control Register 1)......................................................................................................................495
CECRCR2 (Receive Control Register 2)......................................................................................................................497
CECRCR3 (Receive Control Register 3 )....................................................................................................................499
Sampling clock..............................................................................................................................................................508
Reception.......................................................................................................................................................................508
Transmission..................................................................................................................................................................517
Software Reset...............................................................................................................................................................522
CECTEN (Transmit Enable Register).........................................................................................................................501
CECTBUF (Transmit Buffer Register).......................................................................................................................502
CECTCR (Transmit Control Register).......................................................................................................................503
CECRSTAT (Receive Interrupt Status Register).......................................................................................................505
CECTSTAT (Transmit Interrupt Status Register)......................................................................................................506
CECFSSEL(CEC Sampling Clock Select Register)...................................................................................................507
Master mode
Slave mode
Master mode (<MST> = "1")
Slave mode (<MST> = "0")
Clock source
Shift Edge
8-bit transmit mode
8-bit receive mode
8-bit transmit/receive mode
Data retention time of the last bit at the end of transmission
Basic Operation
Preconfiguration
Enabling Reception
Detecting Error Interrupt
Details of reception error
Stopping Reception
Basic Operation
Preconfiguration
Detecting Transmission Error
Details of Transmission Error
Stopping Transmission
Retransmission
xi
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