TMPM362F10FG Toshiba, TMPM362F10FG Datasheet - Page 320

• Manufacturer Part Number: TMPM362F10FG
• Description: 32BIT MICROCONTROLLER
• Manufacturer: Toshiba
• Series: TX03r

Specifications of TMPM362F10FG

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 64MHz
• Connectivity: I²C, Microwire, SIO, SPI, SSP, UART/USART
• Peripherals: DMA, WDT
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 16x10b
• Package / Case: 144-LQFP
• Processor Series: TX03
• Core: ARM Cortex M3
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): 1024K
• Rom Type: Flash
• Ram (kbytes): 64K
• Number Of Pins: 144
• Package: LQFP(20x20)
• Vcc: 3V
• Cpu Mhz: 64
• Ssp (ch) Spi: 1
• I2c/sio (ch): 5
• Uart/sio (ch): 12
• Usb: -
• Can: -
• Ethernet: -
• External Bus Interface: Y
• Cs/wait Controller (ch): 4
• Dma Controller: 2
• 10-bit Da Converter: -
• 10-bit Ad Converter: 16
• 12-bit Ad Converter: -
• 16-bit Timer / Counter: 16
• Motor / Igbt Control: -
• Real Time Clock: 1
• Watchdog Timer: Y
• Osc Freq Detect: -
• Clock Gear: Y
• Low-power Hold Function: Y
• Remote Control Interface: Y
• Hardware Cec Controller: Y
• Comparators: -
• Low-voltage Detector: -
• Etm Hardware Trace: 4-bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Operating Temperature: -
• Number Of I /o: -
• Eeprom Size: -
• Oscillator Type: -
• Lead Free Status / Rohs Status: Details
• Other names: Q5704184A

9.4
Description of Registers
9.4.17
31-19
18
17
16
15
14
13-11
10
9-6
5
bit symbol
After reset
bit symbol
After reset
bit symbol
After reset
bit symbol
After reset
Bit
-
Halt
Active
Lock
ITC
IE
FlowCntrl[2:0]
-
DestPeripheral
[3:0]
-
Bit Symbol
DMACCxConfiguration (DMAC Channelx Configuration Register)
Undefined
Undefined
ITC
31
23
15
0
7
0
-
-
DestPeripheral
W
R/W
R
R/W
R/W
R/W
R/W
W
R/W
W
Type
Undefined
Undefined
30
22
14
IE
0
6
0
-
-
Write as zero.
Controls accepting a DMA request
0 : Accept a DMA request
1 : Ignore a DMA request
Indicates whether data is present in the channel FIFO.
0 : No data exists in the FIFO
1 : Data exists in the FIFO
Sets a locked transfer (Non-divided transfer).
0 : Disable locked transfer
1: Enable locked transfer
When locked transfer is enabled, as many burst transfers as specified are consecutively executed without re-
leasing the bus. For detailed operation, see "9.5 Special Functions".
Terminal count interrupt enable register
0 : Disable interrupts
1 : Enable interrupts
If <ITC> = 1 and DMACCxControl Register<I> = 1 are set, transfer end interrupt occurs.
Error interrupt enable register
0 : Disable interrupts
1 : Enable interrupts
This bit sets the transfer mode.(Note 1)
Write as zero.
Transfer destination peripheral (Note 2)
0000Å`1111
This is a DMA request peripheral number in binary.
This setting will be ignored if memory is specified as the transfer destination.
Write as zero.
<FlowCntrl[2:0]>
011~111:
set value
Undefined
Undefined
Undefined
000:
001:
010:
29
21
13
0
5
-
-
-
Page 296
Undefined
Undefined
FlowCntrl
Memory to Peripheral
Peripheral to Memory
Memory to Memory
28
20
12
0
4
0
-
-
Transfer Mode
Reserved
Undefined
Undefined
Description
27
19
11
0
3
0
-
-
SrcPeripheral
Undefined
Undefined
Halt
26
18
10
0
2
0
-
-
Undefined
Active
25
17
0
9
0
1
0
-
TMPM362F10FG
DestPeripheral
Undefined
Lock
24
16
E
0
8
0
0
0
-