TMPM362F10FG Toshiba, TMPM362F10FG Datasheet - Page 325

• Manufacturer Part Number: TMPM362F10FG
• Description: 32BIT MICROCONTROLLER
• Manufacturer: Toshiba
• Series: TX03r

Specifications of TMPM362F10FG

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 64MHz
• Connectivity: I²C, Microwire, SIO, SPI, SSP, UART/USART
• Peripherals: DMA, WDT
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 16x10b
• Package / Case: 144-LQFP
• Processor Series: TX03
• Core: ARM Cortex M3
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): 1024K
• Rom Type: Flash
• Ram (kbytes): 64K
• Number Of Pins: 144
• Package: LQFP(20x20)
• Vcc: 3V
• Cpu Mhz: 64
• Ssp (ch) Spi: 1
• I2c/sio (ch): 5
• Uart/sio (ch): 12
• Usb: -
• Can: -
• Ethernet: -
• External Bus Interface: Y
• Cs/wait Controller (ch): 4
• Dma Controller: 2
• 10-bit Da Converter: -
• 10-bit Ad Converter: 16
• 12-bit Ad Converter: -
• 16-bit Timer / Counter: 16
• Motor / Igbt Control: -
• Real Time Clock: 1
• Watchdog Timer: Y
• Osc Freq Detect: -
• Clock Gear: Y
• Low-power Hold Function: Y
• Remote Control Interface: Y
• Hardware Cec Controller: Y
• Comparators: -
• Low-voltage Detector: -
• Etm Hardware Trace: 4-bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Operating Temperature: -
• Number Of I /o: -
• Eeprom Size: -
• Oscillator Type: -
• Lead Free Status / Rohs Status: Details
• Other names: Q5704184A

10. Static Memory Controller
10.1
10.2
cess.
TMPM362F10FG contains static memory (NOR type Flash memory and SRAM) controller with asynchronous ac-
Outline function is shown in Table 10-1.
The block diagram of SMC is shown as below.
Note:Execute the WFI instruction after confirming the external memory access is completed.
Function Overview
Block diagram
Table 10-1 Out line function of Static memory Controller
Supported Memory type
and bus connection
Data bus width
Memory map
Timing adjustment
Clock (SMCCLK)
External control signals
Item
Asynchronous access memory (NOR Flash memory, SRAM, etc.)
Multiplex bus and separate bus supported
16bit data bus width
64MB access area is supported and divide into four CS signal and area.
CS0 : 0x6000_0000 to 0x60FF_FFFF (16MB)
CS1 : 0x6100_0000 to 0x61FF_FFFF (16MB)
CS2 : 0x6200_0000 to 0x62FF_FFFF (16MB)
CS3 : 0x6300_0000 to 0x63FF_FFFF (16MB)
Can be controlled AC timing by registers.
fsys / 2
Separate bus :
D0 to D15, A1 to A23, OE, WE, CS0 to CS3, BLS0, BLS1
Multiplex bus :
AD0 to AD15, A17 to A23, OE, WE, ALE, CS0 to CS3, BLS0, BLS1
Page 301
TMPM362F10FG