DF2367VF33 Renesas Electronics America, DF2367VF33 Datasheet - Page 900

• Manufacturer Part Number: DF2367VF33
• Description: MCU 3V 384K 128-QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2300r

Specifications of DF2367VF33

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 33MHz
• Connectivity: I²C, IrDA, SCI, SmartCard
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 84
• Program Memory Size: 384KB (384K x 8)
• Program Memory Type: FLASH
• Ram Size: 24K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 10x10b, D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 128-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Other names: HD64F2367VF33; HD64F2367VF33

Section 24 List of Registers
24.1
The data bus width indicates the numbers of bits by which the register is accessed.
The number of access states indicates the number of states based on the specified reference clock.
Register Name
DTC mode register A
DTC source address register
DTC mode register B
DTC destination address register
DTC transfer count register A
DTC transfer count register B
I
I
I
I
I
Slave address register_0
I
I
I
I
I
I
I
Slave address register_1
I
I
Serial expansion mode register_2
Interrupt priority register A
Interrupt priority register B
Interrupt priority register C
Interrupt priority register D
Rev.6.00 Mar. 18, 2009 Page 840 of 980
REJ09B0050-0600
2
2
2
2
2
2
2
2
2
2
2
2
2
2
C bus control register A_0
C bus control register B_0
C bus mode register_0
C bus interrupt enable register_0
C bus status register_0
C transfer data register_0
C receive data register_0
C bus control register A_1
C bus control register B_1
C bus mode register_1
C bus interrupt enable register_1
C bus status register_1
C transfer data register_1
C receive data register_1
Register Addresses (Address Order)
Abbrevia-
tion
MRA
SAR
MRB
DAR
CRA
CRB
ICCRA_0
ICCRB_0
ICMR_0
ICIER_0
ICSR_0
SAR_0
ICDRT_0
ICDRR_0
ICCRA_1
ICCRB_1
ICMR_1
ICIER_1
ICSR_1
SAR_1
ICDRT_1
ICDRR_1
SEMR_2
IPRA
IPRB
IPRC
IPRD
Bit No. Address Module
8
24
8
24
16
16
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
16
16
16
16
H’BC00
H’BFFF
H'FD58
H'FD59
H'FD5A
H'FD5B
H'FD5C
H'FD5D
H'FD5E
H'FD5F
H'FD60
H'FD61
H'FD62
H'FD63
H'FD64
H'FD65
H'FD66
H'FD67
H'FDA8
H'FE00
H'FE02
H'FE04
H'FE06
to
DTC
DTC
DTC
DTC
DTC
DTC
IIC2_0
IIC2_0
IIC2_0
IIC2_0
IIC2_0
IIC2_0
IIC2_0
IIC2_0
IIC2_1
IIC2_1
IIC2_1
IIC2_1
IIC2_1
IIC2_1
IIC2_1
IIC2_1
SCI_2
INT
INT
INT
INT
Data
Width
16/32
16/32
16/32
16/32
16/32
16/32
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
16
16
16
16
2
2
2
Access
States
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2