DF2367VF33 Renesas Electronics America, DF2367VF33 Datasheet - Page 695

• Manufacturer Part Number: DF2367VF33
• Description: MCU 3V 384K 128-QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2300r

Specifications of DF2367VF33

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 33MHz
• Connectivity: I²C, IrDA, SCI, SmartCard
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 84
• Program Memory Size: 384KB (384K x 8)
• Program Memory Type: FLASH
• Ram Size: 24K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 10x10b, D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 128-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Other names: HD64F2367VF33; HD64F2367VF33

15.3.2
ICCRB is an 8-bit readable/writable register that issues start/stop conditions, manipulates the SDA
pin, monitors the SCL pin, and controls reset in I
Bit Bit Name
7
6
5
4
3
2
1
BBSY
SCP
SDAO
⎯
SCLO
⎯
IICRST
I
2
C Bus Control Register B (ICCRB)
Initial Value R/W
0
1
1
1
1
1
0
R/W
W
R/W
R/W
R
⎯
R/W
Description
Bus Busy
This bit enables to confirm whether the I
or released and to issue start and stop conditions in master
mode. This bit is set to 1 when the SDA level changes from
high to low under the condition of SCL = high, assuming
that the start condition has been issued. This bit is cleared
to 0 when the SDA level changes from low to high under
the condition of SCL = high, assuming that the stop
condition has been issued. Write 1 to BBSY and 0 to SCP
to issue a start condition. Follow this procedure when also
re-transmitting a start condition. Write 0 to BBSY and 0 to
SCP to issue a stop condition. To issue a start/stop
condition, use the MOV instruction.
Start Condition/Stop Condition Prohibit
The SCP bit controls the issue of start/stop conditions in
master mode.
To issue a start condition, write 1 in BBSY and 0 in SCP. A
retransmit start condition is issued in the same way. To
issue a stop condition, write 0 in BBSY and 0 in SCP. This
bit is always read as 1. If 1 is written, the data is not stored.
Monitors the output level of SDA.
0: When reading, SDA pin outputs low.
1: When reading, SDA pin outputs high.
The write value should always be 1.
Reserved
The write value should always be 1.
This bit monitors SCL output level. When reading and
SCLO is 1, SCL pin outputs high. When reading and SCLO
is 0, SCL pin outputs low.
Reserved
This bit is always read as 1.
IIC control part reset
This bit resets control parts except for I
bit is set to 1 when hang-up is occurred because of
communication failure during I
can be reset without setting ports and initializing registers.
2
C control.
Section 15 I
Rev.6.00 Mar. 18, 2009 Page 635 of 980
2
C Bus Interface2 (IIC2) (Option)
2
C operation, I
2
C registers. If this
2
REJ09B0050-0600
C bus is occupied
2
C control part