DF2367VF33 Renesas Electronics America, DF2367VF33 Datasheet - Page 689

• Manufacturer Part Number: DF2367VF33
• Description: MCU 3V 384K 128-QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2300r

Specifications of DF2367VF33

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 33MHz
• Connectivity: I²C, IrDA, SCI, SmartCard
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 84
• Program Memory Size: 384KB (384K x 8)
• Program Memory Type: FLASH
• Ram Size: 24K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 10x10b, D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 128-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Other names: HD64F2367VF33; HD64F2367VF33

An I
item:
For the masked ROM version, ‘W’ is added to the model name of the product that uses optional
functions.
For example: HD6432365WTE
This LSI has a two-channel I
The I
(inter-IC bus) interface (Rev.03) standard and fast mode functions. The register configuration that
controls the I
Figure 15.1 shows a block diagram of the I
Figure 15.2 shows an example of I/O pin connections to external circuits.
15.1
• Continuous transmission/reception
• Start and stop conditions generated automatically in master mode
• Selection of acknowledge output levels when receiving
• Automatic loading of acknowledge bit when transmitting
• Bit synchronization/wait function
• Six interrupt sources
• Direct bus drive
IFIIC40_000020020100
Since the shift register, transmit data register, and receive data register are independent from
each other, the continuous transmission/reception can be performed.
In master mode, the state of SCL is monitored per bit, and the timing is synchronized
automatically
If transmission/reception is not yet possible, set the SCL to low until preparations are
completed.
⎯ Transmit-data-empty (including slave-address match), transmit-end, receive-data-full
⎯ Two pins, SCL and SDA pins function as NMOS open-drain outputs.
2
C bus interface is an option. When using the optional functions, take notice of the following
2
C bus interface conforms to and provides a subset of the NXP Semiconductors I
(including slave-address match), arbitration lost, NACK detection, and stop condition
detection
Features
Section 15 I
2
C bus differs partly from the NXP Semiconductors configuration, however.
2
C bus interface,
2
C Bus Interface2 (IIC2) (Option)
2
C bus interface2.
Section 15 I
Rev.6.00 Mar. 18, 2009 Page 629 of 980
2
C Bus Interface2 (IIC2) (Option)
REJ09B0050-0600
2
C bus