DF2367VF33 Renesas Electronics America, DF2367VF33 Datasheet - Page 720

• Manufacturer Part Number: DF2367VF33
• Description: MCU 3V 384K 128-QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2300r

Specifications of DF2367VF33

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 33MHz
• Connectivity: I²C, IrDA, SCI, SmartCard
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 84
• Program Memory Size: 384KB (384K x 8)
• Program Memory Type: FLASH
• Ram Size: 24K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 10x10b, D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 128-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Other names: HD64F2367VF33; HD64F2367VF33

Section 15 I
3. I
4. Limitations on transfer rate setting values when using I
5. Limitations on use of bit manipulation instructions to set MST and TRS when using I
Rev.6.00 Mar. 18, 2009 Page 660 of 980
REJ09B0050-0600
When operating in master receive mode with RDRF set to 1, SCL is driven low at the falling
edge of the eighth clock cycle. However, when ICDRR is read near the falling edge of the
eighth clock cycle, SCL is only fixed low for one clock cycle at the eighth clock cycle of the
next receive data, after which SCL is no longer fixed and the ninth clock cycle is output, even
if ICDRR is not read. This causes the receive data to overflow.
The following methods can be used to prevent this from occurring.
⎯ In master receive mode, complete processing to read ICDRR before the rising edge of the
⎯ In master receive mode, set RCVD to 1 and perform communication processing one byte at
master mode
When operating in multi-master mode and the IIC transfer rate setting of the MCU is slower
than that of another master device, an SCL of an unanticipated width may by output
occasionally. To prevent this, set the transfer rate to a value 1/1.8 or greater than the fastest
transfer rate among the other master devices. For example, if the fastest transfer rate setting
among the other master devices is 400 kbps, set the IIC transfer rate of the MCU to 223 kbps
(400/1.8) or higher.
interface 2 (IIC2) in multi-master mode
When bit manipulation instructions are used to set MST and TRS in succession to specify
master transmit while operating in multi-master mode, an arbitration lost may occur, during
execution of the bit manipulation instruction to set TRS, with timing that results in a
contradictory state in which AL in ICSR is set to 1 and master transmit mode (MST = 1, TRS
= 1) is selected as well.
The following methods can be used to prevent this from occurring.
⎯ When operating in multi-master mode, always use the MOV instruction to set MST and
⎯ When an arbitration lost occurs, confirm that MST and TRS are both cleared to 0. If the
2
C bus interface 2 (IIC2) master receive mode
eighth clock cycle.
a time.
TRS.
settings are other than MST = 0, TRS = 0, clear MST and TRS to 0.
2
C Bus Interface2 (IIC2) (Option)
2
C bus interface 2 (IIC2) in multi-
2
C bus