DF2367VF33 Renesas Electronics America, DF2367VF33 Datasheet - Page 159

• Manufacturer Part Number: DF2367VF33
• Description: MCU 3V 384K 128-QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2300r

Specifications of DF2367VF33

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 33MHz
• Connectivity: I²C, IrDA, SCI, SmartCard
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 84
• Program Memory Size: 384KB (384K x 8)
• Program Memory Type: FLASH
• Ram Size: 24K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 10x10b, D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 128-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Other names: HD64F2367VF33; HD64F2367VF33

5.3.5
ISR is an IRQ7 to IRQ0 interrupt request flag register.
Note:
Bit
15 to 8
7
6
5
4
3
2
1
0
*
IRQ Status Register (ISR)
Only 0 can be written, to clear the flag.
Bit
Name
−
IRQ7F
IRQ6F
IRQ5F
IRQ4F
IRQ3F
IRQ2F
IRQ1F
IRQ0F
Initial Value
All 0
0
0
0
0
0
0
0
0
R/(W) *
R/(W) *
R/(W) *
R/(W) *
R/(W) *
R/(W) *
R/(W) *
R/(W) *
R/W
R/W
Reserved
The write value should always be 0.
[Setting condition]
When the interrupt source selected by ISCR
occurs
[Clearing conditions]
•
•
•
•
Description
Cleared by reading IRQnF flag when
IRQnF = 1, then writing 0 to IRQnF flag
When interrupt exception handling is
executed when low-level detection is set
and IRQn input is high
When IRQn interrupt exception handling is
executed when falling, rising, or both-edge
detection is set
When the DTC is activated by an IRQn
interrupt, and the DISEL bit in MRB of the
DTC is cleared to 0
Rev.6.00 Mar. 18, 2009 Page 99 of 980
Section 5 Interrupt Controller
REJ09B0050-0600