DF2367VF33 Renesas Electronics America, DF2367VF33 Datasheet - Page 713
DF2367VF33
Manufacturer Part Number
DF2367VF33
Description
MCU 3V 384K 128-QFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2300r
Datasheet
1.DF2368VTE34V.pdf
(1044 pages)
Specifications of DF2367VF33
Core Processor
H8S/2000
Core Size
16-Bit
Speed
33MHz
Connectivity
I²C, IrDA, SCI, SmartCard
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
84
Program Memory Size
384KB (384K x 8)
Program Memory Type
FLASH
Ram Size
24K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 10x10b, D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
128-QFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Other names
HD64F2367VF33
HD64F2367VF33
HD64F2367VF33
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15.4.6
The logic levels at the SCL and SDA pins are routed through noise cancelers before being latched
internally. Figure 15.13 shows a block diagram of the noise canceler circuit.
The noise canceler consists of two cascaded latches and a match detector. The SCL (or SDA)
input signal is sampled on the system clock, but is not passed forward to the next circuit unless the
outputs of both latches agree. If they do not agree, the previous value is held.
15.4.7
Flowcharts in respective modes that use the I
SCL or SDA
input signal
Sampling
clock
Noise Canceler
Example of Use
Figure 15.13 Block Diagram of Noise Canceler
Sampling clock
D
System clock
period
Latch
C
Q
D
2
C bus interface are shown in figures 15.14 to 15.17.
Latch
C
Section 15 I
Q
Rev.6.00 Mar. 18, 2009 Page 653 of 980
March detector
2
C Bus Interface2 (IIC2) (Option)
REJ09B0050-0600
SCL or SDA
Internal
signal
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