DF2367VF33 Renesas Electronics America, DF2367VF33 Datasheet - Page 46

• Manufacturer Part Number: DF2367VF33
• Description: MCU 3V 384K 128-QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2300r

Specifications of DF2367VF33

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 33MHz
• Connectivity: I²C, IrDA, SCI, SmartCard
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 84
• Program Memory Size: 384KB (384K x 8)
• Program Memory Type: FLASH
• Ram Size: 24K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 10x10b, D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 128-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Other names: HD64F2367VF33; HD64F2367VF33

Figure 10.10 Example of Synchronous Operation Setting Procedure ......................................... 446
Figure 10.11 Example of Synchronous Operation....................................................................... 447
Figure 10.12 Compare Match Buffer Operation.......................................................................... 448
Figure 10.13 Input Capture Buffer Operation ............................................................................. 448
Figure 10.14 Example of Buffer Operation Setting Procedure.................................................... 449
Figure 10.15 Example of Buffer Operation (1) ........................................................................... 450
Figure 10.16 Example of Buffer Operation (2) ........................................................................... 451
Figure 10.17 Cascaded Operation Setting Procedure .................................................................. 452
Figure 10.18 Example of Cascaded Operation (1)....................................................................... 453
Figure 10.19 Example of Cascaded Operation (2)....................................................................... 453
Figure 10.20 Example of PWM Mode Setting Procedure ........................................................... 456
Figure 10.21 Example of PWM Mode Operation (1) .................................................................. 457
Figure 10.22 Example of PWM Mode Operation (2) .................................................................. 457
Figure 10.23 Example of PWM Mode Operation (3) .................................................................. 458
Figure 10.24 Example of Phase Counting Mode Setting Procedure............................................ 460
Figure 10.25 Example of Phase Counting Mode 1 Operation ..................................................... 461
Figure 10.26 Example of Phase Counting Mode 2 Operation ..................................................... 462
Figure 10.27 Example of Phase Counting Mode 3 Operation ..................................................... 463
Figure 10.28 Example of Phase Counting Mode 4 Operation ..................................................... 464
Figure 10.29 Phase Counting Mode Application Example.......................................................... 465
Figure 10.30 Count Timing in Internal Clock Operation ............................................................ 469
Figure 10.31 Count Timing in External Clock Operation ........................................................... 469
Figure 10.32 Output Compare Output Timing ............................................................................ 470
Figure 10.33 Input Capture Input Signal Timing ........................................................................ 470
Figure 10.34 Counter Clear Timing (Compare Match) ............................................................... 471
Figure 10.35 Counter Clear Timing (Input Capture) ................................................................... 471
Figure 10.36 Buffer Operation Timing (Compare Match) .......................................................... 472
Figure 10.37 Buffer Operation Timing (Input Capture) .............................................................. 472
Figure 10.38 TGI Interrupt Timing (Compare Match) ................................................................ 473
Figure 10.39 TGI Interrupt Timing (Input Capture).................................................................... 474
Figure 10.40 TCIV Interrupt Setting Timing............................................................................... 475
Figure 10.41 TCIU Interrupt Setting Timing............................................................................... 475
Figure 10.42 Timing for Status Flag Clearing by CPU ............................................................... 476
Figure 10.43 Timing for Status Flag Clearing by DTC/DMAC* Activation .............................. 476
Figure 10.44 Phase Difference, Overlap, and Pulse Width in Phase Counting Mode ................. 477
Figure 10.45 Contention between TCNT Write and Clear Operations........................................ 478
Figure 10.46 Contention between TCNT Write and Increment Operations ................................ 479
Figure 10.47 Contention between TGR Write and Compare Match ........................................... 480
Figure 10.48 Contention between Buffer Register Write and Compare Match........................... 480
Figure 10.49 Contention between TGR Read and Input Capture ................................................ 481
Rev.6.00 Mar. 18, 2009 Page xliv of lviii
REJ09B0050-0600