DF2367VF33 Renesas Electronics America, DF2367VF33 Datasheet - Page 53

• Manufacturer Part Number: DF2367VF33
• Description: MCU 3V 384K 128-QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2300r

Specifications of DF2367VF33

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 33MHz
• Connectivity: I²C, IrDA, SCI, SmartCard
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 84
• Program Memory Size: 384KB (384K x 8)
• Program Memory Type: FLASH
• Ram Size: 24K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 10x10b, D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 128-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Other names: HD64F2367VF33; HD64F2367VF33

Section 1 Overview
Table 1.1
Table 1.2
Section 2 CPU
Table 2.1
Table 2.2
Table 2.3
Table 2.4
Table 2.5
Table 2.6
Table 2.7
Table 2.8
Table 2.9
Table 2.10
Table 2.11
Table 2.12
Table 2.13
Section 3 MCU Operating Modes
Table 3.1
Table 3.2
Section 4 Exception Handling
Table 4.1
Table 4.2
Table 4.3
Table 4.4
Section 5 Interrupt Controller
Table 5.1
Table 5.2
Table 5.3
Table 5.4
Table 5.5
Pin Arrangement in Each Operating Mode ............................................................
Pin Functions.......................................................................................................... 14
Instruction Classification........................................................................................ 37
Operation Notation ................................................................................................. 38
Data Transfer Instructions ...................................................................................... 39
Arithmetic Operations Instructions ........................................................................ 40
Logic Operations Instructions ................................................................................ 42
Shift Instructions .................................................................................................... 42
Bit Manipulation Instructions................................................................................. 43
Branch Instructions................................................................................................. 45
System Control Instructions ................................................................................... 46
Block Data Transfer Instructions............................................................................ 47
Addressing Modes.................................................................................................. 49
Absolute Address Access Ranges .......................................................................... 51
Effective Address Calculation................................................................................ 53
MCU Operating Mode Selection............................................................................ 57
Pin Functions in Each Operating Mode.................................................................. 62
Exception Types and Priority ................................................................................. 79
Exception Handling Vector Table .......................................................................... 80
Status of CCR and EXR after Trace Exception Handling ...................................... 84
Status of CCR and EXR after Trap Instruction Exception Handling ..................... 85
Pin Configuration ................................................................................................... 91
Interrupt Sources, Vector Addresses, and Interrupt Priorities ................................ 103
Interrupt Control Modes......................................................................................... 108
Interrupt Response Times....................................................................................... 114
Number of States in Interrupt Handling Routine Execution Statuses..................... 115
Tables
Rev.6.00 Mar. 18, 2009 Page li of lviii
REJ09B0050-0600
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