DF2367VF33 Renesas Electronics America, DF2367VF33 Datasheet - Page 394

• Manufacturer Part Number: DF2367VF33
• Description: MCU 3V 384K 128-QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2300r

Specifications of DF2367VF33

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 33MHz
• Connectivity: I²C, IrDA, SCI, SmartCard
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 84
• Program Memory Size: 384KB (384K x 8)
• Program Memory Type: FLASH
• Ram Size: 24K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 10x10b, D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 128-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Other names: HD64F2367VF33; HD64F2367VF33

Section 9 I/O Ports
• P12/PO10/TIOCC0/TCLKA/TEND0
Notes: 1. TIOCC0 input when MD3 to MD0 = B'0000 and IOC3 to IOC0 = B'10××.
Legend:
×: Don’t care
Note:
Rev.6.00 Mar. 18, 2009 Page 334 of 980
REJ09B0050-0600
TPU channel 0
settings
MD3 to MD0
IOC3 to IOC0
CCLR2, CCLR0
Output function
TEE0
TPU channel 2
settings
P12DDR
NDER10
Pin function
The pin function is switched as shown below according to the combination of the TPU channel
0 settings (by bits MD3 to MD0 in TMDR_0, bits IOC3 to IOC0 in TIORL_0, and bits CCLR2
to CCLR0 in TCR_0), bits TPSC2 to TPSC0 in TCR_0 to TCR_5, bit NDER10 in NDERH,
bit TEE0 in DMATCR of DMAC and bit P12DDR.
3. TIOCD0 output disabled.
2. TCLKA input when the setting for any of TCR_0 to TCR_5 is TPSC2 to TPSC0 = B'100.
TCLKA input when phase counting mode is set for channels 1 and 5.
Output disabled and settings (2) effective when BFA = 1 or BFB = 1 in TMDR_0.
(1) in table below
TIOCO0 output
B'0000
B'0100
B'1×××
(2)
—
—
—
—
B'0000
B'0001 to
B'0101 to
compare
B'0011
B'0111
Output
output
(1)
—
P12 input
—
0
B'001×
B'××00
(2)
—
—
0
TCLKA input *
(2) in table below
TIOCC0 input *
P12 output
than B'××00
1
0
mode 1
PWM *
B'0010
output
Other
(1)
—
2
3
1
PO10 output
PWM mode
Other than
2 output
1
1
B'101
Other than B'××00
(1)
B'0011
TEND0
output
B'101
—
—
—
(2)
1
—