DF2367VF33 Renesas Electronics America, DF2367VF33 Datasheet - Page 878

• Manufacturer Part Number: DF2367VF33
• Description: MCU 3V 384K 128-QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2300r

Specifications of DF2367VF33

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 33MHz
• Connectivity: I²C, IrDA, SCI, SmartCard
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 84
• Program Memory Size: 384KB (384K x 8)
• Program Memory Type: FLASH
• Ram Size: 24K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 10x10b, D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 128-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Other names: HD64F2367VF33; HD64F2367VF33

Section 22 Clock Pulse Generator
Table 22.3 External Clock Input Conditions
Item
External clock input
low pulse width
External clock input
high pulse width
External clock rise time
External clock fall time
Clock low pulse width
Clock high pulse width
22.3
The PLL circuit has the function of multiplying the frequency of the clock from the oscillator by a
factor of 1, 2, or 4. The multiplication factor is set with the STC1 and the STC0 bits in PLLCR.
The phase of the rising edge of the internal clock is controlled so as to match that of the rising
edge of the EXTAL pin.
When the multiplication factor of the PLL circuit is changed, the operation varies according to the
setting of the STCS bit in SCKCR.
When STCS = 0, the setting becomes valid after a transition to software standby mode. The
transition time count is performed in accordance with the setting of bits STS3 to STS0 in SBYCR.
For details on SBYCR, refer to section 23.1.1, Standby Control Register (SBYCR).
1. The initial PLL circuit multiplication factor is 1.
Rev.6.00 Mar. 18, 2009 Page 818 of 980
REJ09B0050-0600
PLL Circuit
EXTAL
t
EXr
Figure 22.5 External Clock Input Timing
Symbol
t
t
t
t
t
t
EXL
EXH
EXr
EXf
CL
CH
t
EXH
V
to 3.6 V
Min
15
15
—
—
0.4
0.4
CC
= 3.0 V
5
5
0.6
0.6
Max
—
—
t
EXf
t
EXL
ns
ns
ns
ns
t
t
Unit
cyc
cyc
V
CC
Test
Conditions
Figure 22.5
× 0.5