DF2367VF33 Renesas Electronics America, DF2367VF33 Datasheet - Page 715

• Manufacturer Part Number: DF2367VF33
• Description: MCU 3V 384K 128-QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2300r

Specifications of DF2367VF33

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 33MHz
• Connectivity: I²C, IrDA, SCI, SmartCard
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 84
• Program Memory Size: 384KB (384K x 8)
• Program Memory Type: FLASH
• Ram Size: 24K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 10x10b, D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 128-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Other names: HD64F2367VF33; HD64F2367VF33

Note: * Prevent any interrupts while steps [1] to [3] are executed.
Additional information: When receiving one-byte data, execute step [1], and then step [7] omitting steps [2] to [6].
No
No
No
Set ACKBT = 0 (ICIER)
Set ACKBT = 1 (ICIER)
Set RCVD = 0 (ICCRA)
Set RCVD - 1 (ICCRA)
Clear ACKBT of ICIER
Set TRS = 0 (ICCRA)
Set MST = 0 (ICCRA)
Clear TDRE of ICSR
Dummy read ICDRR
Read RDRF in ICSR
Read RDRF in ICSR
Clear STOP of ICSR
Read STOP of ICSR
Clear TEND in ICSR
Mater receive mode
Write BBSY = 0
Read ICDRR
Read ICDRR
Read ICDRR
(Last receive
and SCP = 0
RDRF=1 ?
RDRF=1 ?
STOP=1 ?
Figure 15.15 Sample Flowchart for Master Receive Mode
- 1)?
End
Yes
Yes
Yes
No
In step [8], dummy read ICDRR.
Yes
[1]
[2]
[3]
[4]
[5]
[6]
[7]
[8]
[9]
[10]
[11]
[12]
[13]
[14]
[15]
[16]
[1]
[2]
[3]
[4]
[5]
[6]
[7]
[8]
[9]
[10] Clear STOP flag.
[11] Stop condition issuance
[12] Wait for the creation of stop condition.
[13] Read the receive data of the final byte, and clear RDRF to 0.
[14] Clear RCVD to 0.
[15] Clear ACKBT.
[16] Set slave receive mode.
Clear TEND, select master receive mode, and then clear TDRE. *
Set acknowledge to the transmitting device. *
Dummy read ICDDR *
Wait for 1 byte to be received.
Check if (last receive - 1)
Read the receive data, and clear RDRF to 0.
Set acknowledge of the final byte. Disable continuous receive (RCVD = 1).
Read receive data of (final byte - 1), and clear RDRF to 0.
Wait for the final byte to be received.
Section 15 I
Rev.6.00 Mar. 18, 2009 Page 655 of 980
2
C Bus Interface2 (IIC2) (Option)
REJ09B0050-0600