DF2367VF33 Renesas Electronics America, DF2367VF33 Datasheet - Page 819
DF2367VF33
Manufacturer Part Number
DF2367VF33
Description
MCU 3V 384K 128-QFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2300r
Datasheet
1.DF2368VTE34V.pdf
(1044 pages)
Specifications of DF2367VF33
Core Processor
H8S/2000
Core Size
16-Bit
Speed
33MHz
Connectivity
I²C, IrDA, SCI, SmartCard
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
84
Program Memory Size
384KB (384K x 8)
Program Memory Type
FLASH
Ram Size
24K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 10x10b, D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
128-QFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Other names
HD64F2367VF33
HD64F2367VF33
HD64F2367VF33
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9. All interrupts and the use of a bus master other than the CPU are prohibited.
10. FKEY must be set to H'5A and the user MAT must be prepared for programming.
11. The parameter which is required for programming is set.
12. Programming
The specified voltage is applied for the specified time when programming or erasing. If
interrupts occur or the bus mastership is moved to other than the CPU during this time, the
voltage for more than the specified time will be applied and flash memory may be damaged.
Therefore, interrupts, movement of bus mastership to other than the CPU (DMAC, DTC, or
1set to B'1 in interrupt control mode 0 or bits 2 to 0 (I2 to I0) in the extend control register of
the CPU should be set to B'111 in interrupt control mode 2. Then interrupts other than NMI are
held and are not executed.
The NMI interrupts must be masked within the user system.
The interrupts that are held must be executed after all program processing.
When the bus mastership is moved to other than the CPU by the DMAC, DTC, or BREQ
signal or DRAM refresh cycles are entered, the error protection state is entered. Therefore,
taking bus mastership by the DMAC, DTC, or BREQ signal is prohibited.
The start address of the programming destination of the user MAT (FMPAR) is set to general
register ER1. The start address of the program data area (FMPDR) is set to general register
ER0.
⎯ Example of the FMPAR setting
⎯ Example of the FMPDR setting
There is an entry point of the programming program in the area from the start address specified
by FTDAR + 16 bytes of the on-chip RAM. The subroutine is called and programming is
executed by using the following steps.
MOV.L
JSR
NOP
FMPAR specifies the programming destination address. When an address other than one in
the user MAT area is specified, even if the programming program is executed,
programming is not executed and an error is returned to the return value parameter FPFR.
Since the unit is 128 bytes, the lower eight bits (A7 to A0) must be H'00 or H'80 as the
boundary of 128 bytes.
When the storage destination of the program data is flash memory, even if the program
execution routine is executed, programming is not executed and an error is returned to the
FPFR parameter. In this case, the program data must be transferred to the on-chip RAM
and then programming must be executed.
#DLTOP+16,ER2;
@ER2;
Set entry address to ER2
Call programming routine
Section 20 Flash Memory (0.18-μm F-ZTAT Version)
Rev.6.00 Mar. 18, 2009 Page 759 of 980
REJ09B0050-0600
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